A 272–341-GHz Integrated Amplifier-Frequency-Doubler Chain in 65-nm CMOS

Abstract

This letter presents the development of a wideband amplifier-frequency-doubler chain (AFDC) operating at around 300 GHz based on a 65-nm CMOS technology. A new output matching technique for the frequency doubler (FD) is proposed, which provides extensively improved bandwidth and output power compared to a conventional approach often used. In addition, a five-stage transformer-based differential power amplifier has been developed that precedes the FD for sufficient input power and improved overall conversion gain. The integrated AFDC exhibited a measured peak output power of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 3.0 dBm along with a 3-dB bandwidth of 69 GHz (272–341 GHz) or a fractional bandwidth of 22%. The measured peak conversion gain is 3.8 dB and the power consumption is 159.6 mW. The chip size is 660 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 155 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula> m excluding probing pads.