Tri-material Gate Research Articles

Dual material tri-gate Schottky barrier FET as label free biosensor

In this work, the Dual Material Tri Gate Schottky Barrier Field Effect Transistor (DM-TG-SB-FET) is designed and explored for the biosensing applications. The device uses two different materials of gates and the cavities are created near drain-channel and source-channel junction under gates. The biomolecules with dielectric constant K = 5 to K = 12 have been filled in the cavities and the change has been sensed in the device parameters that are electrical in nature. The sensing parameters have been calculated and compared with the already existing Dielectric Modulated FET based biosensor and a significant improvement has been seen in the DM-TG-SB-FET biosensor. The ION sensitivity, gm sensitivity, SS sensitivity, fT sensitivity has been calculated as 28.41, 13.44, 209 (mV/decade), 30.58 × 1011 Hz, respectively, for the biomolecule having dielectric constant, K = 12 in the proposed DM-TG-SB-FET. Also, the change in potential and energy band diagrams has been seen for different dielectric constants that has led to the change in the electrical parameters of the device.

Analytical modeling approach to drain current characterization of ionization irradiated dual material trigate TFET

Drain current modeling of dual material (DM) trigate TFET under the influence of radiation induced defects characterized by oxide trapped charges and ionized interface traps is formulated in this present research endeavor. An analytical methodology incorporating three dimensional Poisson's equation and Kane's approach introducing the impact of charge traps is derived here to explore the radiation response of the device. Radiation induced device characterization is then investigated in terms of electrostatic potential distribution, electric field profile and drain current performance of DM trigate TFET. Charge trapping and device parameters variation are further examined to capture the device response to radiation effect. Relevant simulated data extracted by ATLAS device simulator is used to substantiate the derived analytical model presented in this paper.

Gate Work Function Engineered Trigate MOSFET with a Dual-Material Bottom Gate for Biosensing Applications: a Dielectric-Modulation Based Approach

Mathematical model development of a Dielectric-Modulated Dual Material Trigate MOSFET with a dual material bottom gate has been introduced for application as a biosensor for detection of biomolecules like enzymes, cell, DNA etc. With solution of 3-D Poisson’s equation, electrical features of the proposed device have been acquired and corresponding shift in the device features due to change in permittivity, charge etc. by the biomolecules implies the type of biomolecule introduced in the nanogap. Further simulation results from Atlas corroborate the analytical results.

Performance Investigation of Gate Engineered tri-Gate SOI TFETs with Different High-K Dielectric Materials for Low Power Applications

In this article, a three-dimensional model of Tri-gate Tunnel Filed effect transistors (TFET) with different gate materials is proposed. Analysis and comparison of various structures such as single material gate, double material gate and triple material gate of a Tri-gate TFET is performed with respect to both DC and AC characteristics. Various electrical parameters that define the performance of a semiconductor device are verified using Silvaco TCAD Simulation results. Parameters analyzed in this work include surface potential, lateral electric field, total electric field along the channel, drain current, transconductance and output conductance of single material, double material and triple material Tri-gate TFETs. The comparative performance analysis shows a better DC and AC performance for Triple Material Tri-gate TFET (TMTGTFET) in comparison to single material and double material Tri-gate devices. It could be inferred that short channel effects are considerably reduced in a gate engineered Tri-Gate TFET structure and it also shows remarkable improvement in ON current as the current increases 45% for TMTGTFET when compared to a SMTG TFET. To improve the TMTGTFET performance, different dielectric materials are employed for device characteristics.

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

AbstractThe semiconductor industry has implemented the technique of wrapping the gate electrode on different sides of channel to mitigate the degrading electrostatic effects in nanometer transistor. Intel adopted trigate architecture, wherein the channel is surrounded by gate electrode on three sides to improve the gate control over the channel. In order to further enhance the performance and diminish the short channel effects, triple material trigate silicon‐on‐insulator (SOI) MOSFET is explored in this work. An analytical model to determine the device electrostatics and match deviations due to device geometry has also been developed. The consequence of quantum confinement effects (QMEs), which arise due to ultra‐thin body structure, on the inversion charge and threshold voltage has also been included. Thus, the analytical model presented in this work is based on a self‐consistent solution of three‐dimensional Poisson's equation and two‐dimensional Schrodinger equation with proper boundary conditions. The model is verified by the uniformity obtained between the results from analytical model and TCAD simulations. The superiority of the device has been demonstrated by comparing performance parameters like potential distribution, field variations, drain induced barrier lowering (DIBL) with already existing device structures like single material trigate (SMTG) and dual material trigate (DMTG) SOI MOSFETs

Simulation study of hetero dielectric tri material gate tunnel FET based common source amplifier circuit

Tunneling Field Effect Transistor (TFET) has emerged as an alternative device to MOSFET for designing low power analog and digital integrated circuits. This paper investigates the performance of a common source amplifier circuit designed using Gate-All-Around Hetero Dielectric Tri Material Gate TFET device. HD-TMGTFET device is designed on Visual TCAD tool and a look up table-based Verilog A model has been designed to perform SPICE circuit simulations. The performance of the HD-TMGTFET based CS amplifier circuit is compared with the MOSFET based amplifier designed using 65 nm MOSFET device. Device simulation results show that HD-TMGTFET device exhibits steep subthreshold slope of 21.2 mV/decade, high ON current of 7.5 × 10−6 A/µm and extremely low OFF state current of the order of 10−19 A/µm. The device also exhibits extremely low values of miller capacitances and has maximum unity gain frequency of 124 GHz at gate voltage of 0.9 V. HD-TMGTFET device based amplifier can provide amplification of up to 3 times within the frequency range of 100 KHz to 0.1 GHz and on the other hand MOSFET based amplifier circuit provides amplification up to 1.58 times over limited frequency range of 1 MHz, clearly showing the potential of using HD-TMGTFET device in high frequency applications.

3D modelling based comprehensive analysis of high-κ gate stack graded channel dual material trigate MOSFET * * Project supported by the Ministry of Electronics and Information Technology (MEITy), Govt. of India under its Visvesvaraya PhD Scheme (PhD-MLA/4(55)/2015-16).

The evolution of the traditional metal oxide semiconductor field effect transistor (MOSFET) from planar single gate devices into 3D multiple gates has led to higher package density and high current drive. However, due to continuous scaling and as a consequent close proximity between source and drain in the nano-regime, these multigate devices have been found to suffer from performance degrading short channel effects (SCEs). In this paper, a three dimensional analytical model of a trigate MOSFET incorporating non-conventional structural techniques like silicon-on-insulator, gate and channel engineering in addition to gate oxide stack is presented. The electrostatic integrity and device capability of suppressing SCEs is investigated by deriving the potential distribution profile using the three dimensional Poisson’s equation along with suitable boundary conditions. The other device parameters like threshold voltage and subthreshold swing are produced from the surface potential model. The validity of the proposed structure is established by the close agreement among the results obtained from the analytical model and simulation results.

Design & Optimization of Gate-All-Around Tunnel FET for Low Power Applications

This paper investigates the performance of tri material gate tunnel field effect transistor (TMGTFET) device designed in gate all around (GAA) configuration. The device performance is analyzed by varying various device related parameters like: drain doping, oxide thickness and radius of silicon core. Simulations are performed using technology computer-aided design (TCAD) tool at 60 nm gate length. Simulation results show that the performance of TMGTFET device can be optimized by proper selection of device parameters so as to achieve improvements in the ON current, OFF current, sub-threshold swing and ambipolar current. The silicon based TMGTFET device demonstrates good performance which makes it a suitable candidate for low power applications with ON current of 0.386 µA/µm, average sub-threshold swing of 32.06 mV/decade, maximum current gain cut off frequency of 41.4 GHz and extremely low OFF current value of the order of 10-20A/µm. We have performed the device optimization to boost the ON current and improve the sub-threshold slope in order to make sure that this device configuration becomes suitable for both low power and high performance applications. The proposed hetero dielectric tri material gate tunnel FET device (HD-TFET) designed in gate all around configuration achieves 19.7 times improvement in ON current as compared to TMGTFET device and excellent average sub-threshold swing of 21.2 mV/decade. The maximum unity current gain frequency is also improved by 3 times indicating its potential for deployment in high frequency applications.

3D Modelling and Performance Analysis of Dual Material Tri-Gate Tunnel Field Effect Transistor

ABSTRACTThis work presents a detailed three-dimensional analytical modelling and simulation study of a dual material tri-gate (DM TG) tunnelling field effect transistor (TFET) obtained by intermixing the concepts of tri-gate architecture and dual material gate in the widely popular TFET structure. The proposed model aims to tune the tunnelling barrier in the channel region at the source channel junction so that the band-to-band tunnelling of carriers occurs at a significant rate and reaches the drain region efficiently under the influence of enhanced gate control over the channel region, thereby increasing the device ON current. An overall performance comparison of the proposed DM TG-TFET with that of its single-metal tri-gate (SM TG) TFET counterpart has been depicted to establish the effectiveness of the proposed DM TG-TFET structure. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.

Comparisons between Dual and Tri Material Gate on a 32 nm Double Gate MOSFET

The paper reports a comparative analysis between the dual material gate double gate (DMG-DG) nMOSFET and the tri material gate double gate (TMG-DG) nMOSFET in terms of their analog and RF performance. Three different devices having the DMG-DG structure have been considered. Each of the devices have different higher workfunction material gate length (L1) to lower workfunction material gate length (L2) ratio (L1:L2). Along with the three devices, the performance of the TMG-DG nMOSFET is compared. The analog parameters considered for the comparison are the drain current ([Formula: see text]), the transconductance ([Formula: see text]), the transconductance generation factor ([Formula: see text]/[Formula: see text]) and the intrinsic gain ([Formula: see text]Ro). The drain induced barrier lowering (DIBL) of the devices is compared. The RF analysis is performed using the non quasi static (NQS) approach. We consider the intrinsic gate to source capacitances ([Formula: see text]), the intrinsic gate to drain capacitance ([Formula: see text]), the intrinsic gate to source resistances ([Formula: see text]), the intrinsic gate to drain resistance ([Formula: see text]), the transport delay ([Formula: see text]), the unity current gain cut-off frequency ([Formula: see text]) and the max frequency of oscillation ([Formula: see text]) for the RF comparisons. A single stage amplifier is also implemented using the devices for a circuit comparison.

Modelling and simulation of tri-material gate stack gate all-around (TMGSGAA) MOSFET using Legendre Wavelets for analog/RF applications

In this work, a 2D modelling of tri-material gate stack gate all around (TMGSGAA) MOSFET considering quantum mechanical effects is developed and its analog/RF characteristics are simulated. A self-consistent solution of 2D Poisson-Schrödinger equation has been obtained using Legendre Wavelets. It provides accurate results by performing efficient computation using adaptive mesh obtained by multiresolution approach. The accuracy of the method has been verified with TCAD simulation results. A systematic, quantitative investigation of main figure of merit (FOMs) for the device is carried out to demonstrate its improved RF/analog performance. The results show an improvement in drain current, Ion/Ioff ratio, transconductance, fT and fmax providing superior RF performance under low-power operating conditions.

Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis

The current work reveals the substantial benefits of the various gate and channel engineering concepts, as well as the combination of both on the gate stack double gate (GS-DG) MOSFET. It is demonstrated that post implementation of tri material (TM) gate electrode and halo doping in the channel are significantly alleviated various performance metrics of GS-DG MOSFET. The study is based on surface potential, e-mobility, e-field, threshold voltage (Vth), subthreshold swing (SS), on-current (Ion), off-state current (Ioff), transconductance (gm1), second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order intercept input power (IIP3), intermodulation distortion (IMD3), 1-db compression point, and higher order transconductance coefficients gm2, and gm3. Optimal device design parameters and trade-offs are examined through 2-D Sentaurus device simulator. The results are significant and reliable for RFICs with nanoscale MOSFETs.

Lateral energy band profile modulation in tunnel field effect transistors based on gate structure engineering

Choosing novel materials and structures is important for enhancing the on-state current in tunnel field-effect transistors (TFETs). In this paper, we reveal that the on-state performance of TFETs is mainly determined by the energy band profile of the channel. According to this interpretation, we present a new concept of energy band profile modulation (BPM) achieved with gate structure engineering. It is believed that this approach can be used to suppress the ambipolar effect. Based on this method, a Si TFET device with a symmetrical tri-material-gate (TMG) structure is proposed. Two-dimensional numerical simulations demonstrated that the special band profile in this device can boost on-state performance, and it also suppresses the off-state current induced by the ambipolar effect. These unique advantages are maintained over a wide range of gate lengths and supply voltages. The BPM concept can serve as a guideline for improving the performance of nanoscale TFET devices.

Analytical Threshold Model for Nanoscale Cylindrical Surrounding-Gate Metal–Oxide–Semiconductor Field Effect Transistor with High-κ Gate Dielectric and Tri-Material Gate Stack

A novel cylindrical surrounding-gate metal–oxide–semiconductor field effect transistor with high-κ gate dielectric and tri-material gate stack (TMGCSG MOSFET) is presented. The performance of the new structure is studied by developing physics-based analytical models for surface potential, electric field, and threshold voltage. It is found that TMGCSG MOSFET can effectively suppress short-channel effects and hot-carrier effects, and simultaneously improve carrier transport efficiency. It is also revealed that threshold voltage roll-off for TMGCSG MOSFET can be significantly reduced by adopting both a small effective stack-gate oxide thickness and a small radius silicon channel. The accuracy of the analytical models is verified by its good agreement with the three-dimensional numerical device simulator DESSIS.

A New Two-Dimensional Analytical Model for Nanoscale Symmetrical Tri-Material Gate Stack Double Gate Metal–Oxide–Semiconductor Field Effect Transistors

Based on the resultant solution of two-dimensional (2D) Poisson's equation in silicon region, a new, compact and analytical model for nanoscale fully depleted, symmetrical tri-material gate stack double-gate (STMGSDG) metal–oxide–semiconductor field-effect transistor (MOSFET) has been developed. The STMGSDG MOSFET exhibits significantly reduced short-channel effects (SCEs) when compared with the symmetrical single-material gate stack double-gate (SSMGSDG) MOSFET. It is found that the threshold voltage roll-off for the fully depleted STMGSDG MOSFET can be effectively reduced by using both thin Si film and thin gate oxide. Besides, the high ratio of large work function of metal gate 1 (L1) to the total gate can efficiently suppress the drain-induced barrier lowering (DIBL) and maintain the low threshold voltage degradation. This study not only presents a precise 2D analytical model of the surface potential and threshold voltage, but also discusses the electric field distribution in the channel region, subthreshold swing and subthreshold current for the STMGSDG MOSFET. The new model is verified to be in a good agreement with numerical simulation results over a wide range of the device parameters.

Modeling and simulation of a nanoscale three-region tri-material gate stack (TRIMGAS) MOSFET for improved carrier transport efficiency and reduced hot-electron effects

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture-Tri-Material Gate Stack MOSFET-is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with and without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results