Abstract
The current work reveals the substantial benefits of the various gate and channel engineering concepts, as well as the combination of both on the gate stack double gate (GS-DG) MOSFET. It is demonstrated that post implementation of tri material (TM) gate electrode and halo doping in the channel are significantly alleviated various performance metrics of GS-DG MOSFET. The study is based on surface potential, e-mobility, e-field, threshold voltage (Vth), subthreshold swing (SS), on-current (Ion), off-state current (Ioff), transconductance (gm1), second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order intercept input power (IIP3), intermodulation distortion (IMD3), 1-db compression point, and higher order transconductance coefficients gm2, and gm3. Optimal device design parameters and trade-offs are examined through 2-D Sentaurus device simulator. The results are significant and reliable for RFICs with nanoscale MOSFETs.
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