Mainstream CMOS Technology Research Articles

Vertical C-Shaped-Channel Nanosheet FETs Featured With Precise Control of Both Channel-Thickness and Gate-Length

A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{I}_{\text {on}}/\text {I}_{\text {off}}$ </tex-math></inline-formula> ratio of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${6.28}\times {10}^{{9}}$ </tex-math></inline-formula> were achieved. The device performance and it’s optimization were also investigated with the reduction of the external resistance and numerical simulations.

Room-Temperature Silicon Platform for GHz-Frequency Nanoelectro-Opto-Mechanical Systems.

Nanoelectro-opto-mechanical systems enable the synergistic coexistence of electrical, mechanical, and optical signals on a chip to realize new functions. Most of the technology platforms proposed for the fabrication of these systems so far are not fully compatible with the mainstream CMOS technology, thus, hindering the mass-scale utilization. We have developed a CMOS technology platform for nanoelectro-opto-mechanical systems that includes piezoelectric interdigitated transducers for electronic driving of mechanical signals and nanocrystalline silicon nanobeams for an enhanced optomechanical interaction. Room-temperature operation of devices at 2 GHz and with peak sensitivity down to 2.6 cavity phonons is demonstrated. Our proof-of-principle technology platform can be integrated and interfaced with silicon photonics, electronics, and MEMS devices and may enable multiple functions for coherent signal processing in the classical and quantum domains.

An Interference-Tolerant Synchronization Scheme for Wireless Communication Systems Based on Direct Sequence Spread Spectrum

In this paper, an interference-tolerant three-level synchronization scheme for wireless communication systems based on Direct Sequence Spread Spectrum (DSSS) is presented. Although the proposed synchronization scheme is demonstrated in a mixed signal IC solution, it is exportable to fully digital realizations. The proposed technique synchronizes the received pseudo-random sequence (PRS) modulated signal with the receiver (RX) reference PRS by making use of its autocorrelation properties. The proposed scheme employs 3 levels that make the proposed scheme tolerant to strong in-band interferences. Experimental results for the prototype demonstrate the capabilities of the proposed approach to achieve over 50% of clock cycle tracking even in the presence of interferences with a power of 5dB higher than the desired signal power. Fabricated in a mainstream 40nm CMOS technology, the synchronization scheme employs 100MHz PRS at TX and RX; the proposed solution consumes 18.7mW power and around 0.087mm² silicon area.

Compact modeling of sectorial split-drain magnetic field-effect transistors

Split-drain magnetic field-effect transistor (SD-MAGFET), having the key advantage of possible system integration with the mainstream CMOS technology, should be one of the key technological options for achieving better human and environmental interfacing of digital products as proposed in the More-than-Moore paradigm. However, the characteristics, the potential, and the design methodologies of this new device structure have not fully explored yet. By introducing the effective channel width concept and basing on the first principle of charge transport, we conducted a compact modeling on the magnetic sensitivity of sectorial split-drain MAGFET (SSD-MAGFET). Our model provides some intuitive views on the effects of the devices parameters, such as the sectorial angle, gap width between the two drains, effective aspect ratio, on the operation range and magnetic sensitivity. The model agrees well with the experimental results and suggests that the sensitivity-B field relationship could be approximated by two piecewise linear regions according to the field strength and there exists an optimal sector angle which is governed by the gap width and effective aspect ratio of the SSD-MAGFET.

(Gordon E. Moore Medal for Outstanding Achievement in Solid State Science and Technology Award Address) Towards Silicon-Based Photonic Integrated Circuits: The Quest for Compatible Light Sources

Optoelectronics and photonics are playing an essential role in many aspects of daily life, including information and communication technologies, environmental and green technologies, mechanical and chemical sensing, consumer electronics, and biomedicine. So far, the use of optical components in communication systems has been mainly limited to direct replacement of electrical cables by optical cables. With the continual increase in link bit rates, optical cables are now replacing electrical cables for shorter and shorter interconnect lengths. Optoelectronic and photonic technologies are becoming less costly and more integrated, and there is currently an opportunity for optics to move “inside the box” and change the interconnect topology at all levels. Optical interconnects are required these days for on-chip technology as an alternative to metal wires, because of data transmission bottlenecks introduced by their unavoidable delay times, significant signal degradation, problems with power dissipation, and electromagnetic interference. Such optical interconnects will help in extending the life of Moore’s Law [1]. Currently, most optoelectronic devices are fabricated as discrete components. This approach is based on serial (e.g., step-by-step) fabrication and packaging, and it makes optoelectronic technology drastically different compared to microelectronics, where the domination of parallel fabrication made possible ultra large scale integration. Also, discrete assembly reduces the optoelectronic system reliability and decreases the manufacturing yield. Additional complications arise due to materials issues: in microelectronics the major material is elemental silicon, while traditional semiconductor materials for optoelectronics are III-V compound alloys with much more complex technological requirements. Finally, optical waveguides and waveguide based devices are very bulky compared to electron devices; thus, the densities of electron devices in integrated circuits are many orders of magnitude greater compared to that in integrated optoelectronic systems. Silicon photonics, where photonics devices are fabricated by using silicon or silicon compatible materials and where the manufacturing is based on the available microelectronics infrastructure, is emerging as the technology that can face all these challenges [2]. Silicon photonics is booming and growing at an incredible pace with many breakthroughs appearing day by day [3,4]. Speed, integration density, active components, logic, nonlinear optics, etc., are all surpassed frontiers, which silicon photonics has continuously moved apart. Many devices enabled by silicon photonics are already on the market and new ones are emerging continually [5]. Despite these advances, the major deficiency in such optoelectronic and photonic devices remains the lack of suitable silicon-based light emitters and especially lasers, which would enable a fully integrated silicon platform. In order to be commercially viable, these light emitters need to be efficient, fast, operational at room temperature, and, perhaps most importantly, be compatible with mainstream CMOS technology. Another important requirement is in the emission wavelength, which should match the optical waveguide low-loss spectral region of 1.3–1.6 μm. The main problem in utilizing silicon as a light emitter is its indirect electronic band gap that results in inefficient carrier recombination and a long radiative lifetime. Many quite different approaches to alleviating the miserable light emission in bulk silicon (~10-4 quantum efficiency at 300 K) have been proposed and are actively being explored [6]. Some, such as Si1-xGex quantum well or Si/SiO2 superlattice structures, rely on band structure engineering, while others rely on quantum confinement effects in lower dimensional structures, as typified by silicon quantum dots or porous silicon. Still another approach is impurity-mediated luminescence from, for example, isoelectronic substitution or by the addition of rare earth or transition metal ions to silicon. In this presentation, the use of the quantum confinement approach we have employed to producing efficient light emission in silicon and germanium will be reviewed. Nanostructured systems that will be covered include porous silicon, silicon quantum wells and wires, super unit cells, and arrays of silicon-germanium quantum dots. https://en.wikipedia.org/wiki/Moore%27s_lawL. Pavesi and D.J. Lockwood, Silicon Photonics (Springer, Berlin, 2004).Special issue on Silicon Photonics, Proc. IEEE 97(7), July (2009).D.J. Lockwood and L. Pavesi, Silicon Photonics II: Components and Integration (Springer, Berlin, 2011).L. Pavesi and D.J. Lockwood, Silicon Photonics III: Systems and Applications (Springer, Berlin, 2016).D.J. Lockwood, Light Emission in Silicon (Academic, New York, 1998).

Chip-Scale Molecular Clock

An ultra-stable time-keeping device is presented, which locks its output clock frequency to the rotational-mode transition of polar gaseous molecules. Based on a high-precision spectrometer in the sub-terahertz (THz) range, our new clocking scheme realizes not only fully electronic operation but also implementations using mainstream CMOS technology. Meanwhile, the small wavelength of probing wave and high absorption intensity of our adopted molecules (carbonyl sulfide, 16O12C32S) also enable miniaturization of the gas cell. All these result in an “atomic-clock-grade” frequency reference with small size, power, and cost. This paper provides the architectural and chip-design details of the first proof-of-concept molecular clock using a 65-nm CMOS bulk technology. Using a 231.061-GHz phase-locked loop (PLL) with frequency-shift keying (FSK) modulation and a sub-THz FET detector with integrated lock-in function, the chip probes the accurate transition frequency of carbonyl sulfide (OCS) gas inside a single-mode waveguide, and accordingly adjusts the 80-MHz output of a crystal oscillator. The clock consumes only 66 mW of dc power and has a measured Allan deviation of 3.8 $\times $ 10 $^{-10}$ at an averaging time of $\tau =1000$ s.

A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs

A power-efficient pipeline analog-to-digital converter (ADC) architecture employing a current-mode (CM) multiplying digital-to-analog converter (MDAC) is implemented in this paper. A linear operational transconductance amplifier (OTA), a current steering DAC, and a transimpedance amplifier (TIA) work together as an error amplifier to implement the first stage of the pipeline ADC. The high output impedance displayed by both OTA and MDAC allow us to maximize the power efficiency of the residue amplifier. Compared with a conventional switched-capacitor (SC) MDAC architecture, the proposed CM MDAC reduces the architecture’s power consumption. The fabricated pipeline ADC achieves a 61.3-dB/60.2-dB signal-to-noise and distortion ratio (SNDR) and a 76-dB/74-dB spurious-free dynamic range (SFDR) for a sinusoidal input of 4.15 and 97.9 MHz, respectively. The ADC’s power consumption when operating at 200 MS/s is 8.4 mW, and the conversion figure of merit (FoM) is a 44 fJ/conversion step. The prototype occupies an active area of 0.23 mm2 in a mainstream low-power 40-nm CMOS technology.

OPTICAL PROPERTIES OF SB DOPED GE FILM ON SILICON SUBSTRATE BY MOLECULAR BEAM EPITAXY TECHNIQUE

To enhance the photoluminescence effeciency of the Ge film, we can apply a tensile strain or n doping in the Ge epilayers for modifying it’s energy band gap structure. In this work, we combine both electron doping method from Sb source and inducing a tensile strain in Ge films. Sb doped Ge grown on Si(100) substrate by molecular beam epitaxy technique. The dependence of photoluminescence intensity on the substrate temperature in the range of 130-240oC and on the Sb source temperature from 240 to 300oC are investigated. The active electron concentration obtained up to 2.5x1019cm-3. The tensile strain level in the Sb-doped Ge epilayers is twice larger than that of the P-doped Ge films using GaP solid source or PH3 gas precursor. These results are significant in the realization of the Si based photoelectronic devices which are compatible with mainstream CMOS technology.

Application of a Quantum-Well Silicon NMOS Transistor as a Folding Amplifier Frequency Multiplier

This paper reports on the use of a single quantum well (QW) silicon NMOS transistor to generate a folded current–voltage transfer function that enables frequency doubling and tripling. The QW NMOS device is fabricated entirely on an industrially standard 45 nm technology node CMOS processing line. Quantum transport through the QW results in negative differential transconductances that fold the $I_{DS}$ – $V_{G}$ function. Using two such folds, time domain data shows frequency doubling up through the kHz range at room temperature, and Fourier analysis confirms that the output is dominated by the second harmonic of the input. Total harmonic distortion is approximately -14 dB. De-embedding the frequency response from parasitic cable and contact impedances suggests that the intrinsic doubling bandwidth of a QW NMOS transistor could be as high as 10 GHz if monolithically integrated into a circuit. The high frequency performance of the QW NMOS is limited by the relatively high transresistance magnitude of the device. Frequency tripling can also be shown using a single QW NMOS with three folds. This work helps establish the high frequency performance limitations of a QW NMOS device. It is also the first example of a silicon quantum device fabricated by mainstream CMOS technology being used in a circuit application.

FinFET Devices and Integration

FinFET Devices and Integration

Edge Couplers With Relaxed Alignment Tolerance for Pick-and-Place Hybrid Integration of III–V Lasers With SOI Waveguides

We report on two edge-coupling and power splitting devices for hybrid integration of III-V lasers with sub-micrometric silicon-on-insulator waveguides. The proposed devices relax the horizontal alignment tolerances required to achieve high coupling efficiencies and are suitable for passively aligned assembly with pick-and-place tools. Light is coupled to two on-chip single mode SOI waveguides with almost identical power coupling efficiency, but with a varying relative phase accommodating the lateral misalignment between the laser diode and the coupling devices, and is suitable for the implementation of parallel optics transmitters. Experimental characterization with both a lensed fiber and a Fabry-Pérot semiconductor laser diode has been performed. Excess insertion losses (in addition to the 3 dB splitting) taken as the worst case over both waveguides of respectively 2 ± 0.3 dB and 3.1 ± 0.3 dB, as well as excellent 1 dB loss placement tolerance range of respectively 2.8 μm and 3.8 μm (worst case over both in-plane axes) have been measured for the two devices. Back-reflections to the laser are below -20 dB for both devices within the 1 dB misalignment range. Devices were fabricated with 193 nm DUV optical lithography and are compatible with mass-manufacturing with mainstream CMOS technology.

High speed photodiodes in standard nanometer scale CMOS technology: a comparative study

This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

Ultra-High Tensile Stress Capping Layer Using Novel Excimer Laser Annealing Technology for 32nm nMOSFET and Beyond

A novel processing technology for stressed capping-layer by 248nm KrF excimer laser is reported. The treated tensile capping layer is composed of silicon nitride fabricated by normal PECVD. The effects of laser annealing with different conditions on tensile nitride are extensively investigated. The number of excimer laser pulses is from 3 to 15 and energy density from 500mJ/cm2 to 800mJ/cm2. Different from conventional post-processing techniques applied in current mainstream CMOS technology for tensile SiN curing, the excimer laser annealing demonstrated much higher energy efficency and as a result, the laser annealing broke more silicon-hydrogen and nitrogen-hydrogen bonds within a much shorter time during film curing. The maximum stress of this cured layer is about 2.2GPa through typical Raman spectroscopy measuring, which much larger than that just after tensile nitride film deposition. This new process supplies one of promising solution for stress-enhancement degradation in sub-32nm CMOS technology.

A novel lambda negative-resistance transistor in the 0.5 μm standard CMOS process

A novel negative-resistance transistor (NRT) with a Lambda shaped I–V characteristic is demonstrated in the 0.5 μm standard CMOS process. To save on the number of component devices, this device does not use standard device models provided by CMOS processes, but changes a MOSFET and a BJT into a single device by fabricating them in the same n-well, with a p-type base layer as the MOSFET’s substrate. The NRT has a low valley current of −6.82 nA and a very high peak-to-valley current ratio of 3591. The peak current of the device is −24.49 μA which is low enough to reduce the power consumption of the deivce, and the average value of its negative resistance is about 32 kΩ. Unlike most negative-resistance devices which have been fabricated on compound semiconductor substrates in recent years, this novel NRT is based on a silicon substrate, compatible with mainstream CMOS technology. Our NRT dramatically reduces the number of devices, minimizing the area of the chip, has a low power consumption and thus a further reduction in cost.

High-Speed, Single-Photon Avalanche-Photodiode Imager for Biomedical Applications

The design of a low-light level pixel in CMOS technology for biomedical applications is described. This pixel is also suitable for very high-speed applications, such as fluorescence lifetime imaging (FLIM) used for drug discovery and/or minimally-invasive optical biopsy. In order to achieve high-speed imaging using single-photon detection, a detector with a very low dead-time is needed. The single-photon avalanche-photodiode (SPAD) discussed in this work uses a mainstream deep-submicron CMOS technology in order to achieve ultrahigh-speed operation and high pixel fill-factor, with in-pixel active quench and reset circuits. The paper also presents an innovative approach for reducing the deadtime of the detector and an attractive technique for simultaneous high-speed image acquisition by all the pixels of an array in parallel.

A Novel, High-Dynamic-Range, High-Speed, and High-Sensitivity CMOS Imager Using Time-Domain Single-Photon Counting and Avalanche Photodiodes

Avalanche photodiodes used in Geiger mode as single-photon counters have become very attractive imaging tools. High-speed single-photon imaging can be used in very low-light-level applications such as surveillance and security imaging, quantum computing, and biomedical imaging including bioluminescence and fluorescence lifetime imaging. However, a typical avalanche-based single-photon detector cannot offer the high dynamic range that is needed for many biomedical and surveillance applications. In this paper, we show how a single-photon detector can be used in time domain for high-dynamic-range applications. We also discuss novel techniques to implement the time-domain single-photon imager in mainstream deep-submicrometer CMOS technology. The designed imager offers high dynamic range and high sensitivity, while maintaining high-speed operation and low cost.

(Invited) Growth of MnGe Nanostructures for Spintronics Applications

Mainstream CMOS technology in today's electronics continues to scale down in the feature size. However, power dissipation per unit area and variability are among two major issues and challenges for the continuing scaling. Spintronics, as an emerging technology that exploits the intrinsic spin of the carriers, could potentially offer power savings, low variability and improved scalability. Using nanoscale materials makes possible heterogeneous integration of dissimilar materials by accommodation of strain and minimizing defects. In this paper, we present work on MnxGe1-x nanostructures. We discuss our nanoscale deposition and nano-epi approach in preparing single-crystalline dilute magnetic Mn0.05Ge0.95 QDs. By the use of MOS capacitor with the Mn0.05Ge0.95 QDs as the channel material and by controlling the electrical field at the gate, we demonstrate the ferromagnetism of the QDs by modulating the hole concentration in the channel. A theoretical understanding of high-Curie temperature nature of Mn0.05Ge0.95 is also provided via DOS simulations.

Thermal Noise in MOSFETs: A Two- or a Three-Parameter Noise Model?

In this brief, it is clearly demonstrated that a two-parameter noise model is sufficient to accurately extract the MOSFET high-frequency noise performance, as long as channel uniformity is ensured (which corresponds to mainstream CMOS technology). Nevertheless, in the case of asymmetric channel-based MOSFETs, it is shown that a three-parameter noise model is required.

A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology

The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.

A FinFET and Tri-gate MOSFET's channel structure patterning and its influence on the device performance

A simple and manufacturing worthy method to pattern a very thin channel body of the FinFET/Tri-gate MOSFET is presented. A channel body as thin as 40 nm using the phase-shift mask (PSM) technique with deep UV 248 nm lithography on UV 210 Shipley resist has been achieved, while having an inherently wider Source/Drain (S/D) extension region. The width of extension region was optimized using the Prolitho.3D lithography simulator for the exposure dose and reticle bias conditions. The device simulation of the wider S/D extension region performed using three-dimensional (3-D) Davinci device simulator shows the significant reduction in the S/D parasitic resistance. Furthermore, these patterns on photoresists like UV 210 provides the basis for the easy integration to the mainstream CMOS technology, hence the potential for manufacturability with higher device performance.