Abstract
The design of a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented. The use of stacked devices with a self-biased cascode topology allows the driver to operate at three times the nominal supply voltage. Oxide stress and hot carrier degradation is minimized since the driver operates within the voltage limits imposed by the design rules of a mainstream CMOS technology. The proposed high-voltage architecture uses a switching output stage. The realized prototype delivers an output swing of 6.46 V to a 50-/spl Omega/ load with a 7.5-V supply and an input square wave of 10 MHz. A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz results in an IM3 of -65 dB and an IM2 of -67 dB. The on-resistance is 5.9 /spl Omega/.
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