Magnetic Random Access Memory Research Articles

STT-MRAM-Based Reliable Weak PUF

In recent years, micro-nano device characteristics like ferroelectrics and resistive switching are being used to build important security primitives such as Physical Unclonable Function (PUF). The micro-nano device-based hardware security primitives, although with higher security, energy efficiency, and integration density, suffer from serious reliability issues caused by process scaling. To mitigate this issue, this paper introduces a reconfigurable weak PUF based on spin-transfer torque magnetoresistive random-access memory (STT-MRAM), which adopts the crossing switches implemented with simple demultiplexes (DEMUXs) to improve the flexibility and reliability. Moreover, two algorithms, <monospace>neighboring bit lines</monospace> and <monospace>top-<inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives><mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mi>n</mml:mi></mml:math><inline-graphic xlink:href="hu-ieq1-3095657.gif" xmlns:xlink="http://www.w3.org/1999/xlink"/></alternatives></inline-formula></monospace> , are proposed to enlarge the gap between two parallel reading currents, thus further enhancing the reliability of PUF responses. Experimental results demonstrate that the proposed PUF scheme achieves good uniqueness (50.64 percent), uniformity (50.02 percent), and bit-aliasing ( <inline-formula><tex-math notation="LaTeX">$\approx$</tex-math></inline-formula> 49.80%). Particularly, the proposed method significantly improves the PUF reliability, achieving low bit error rate (BER <inline-formula><tex-math notation="LaTeX">$\leq$</tex-math></inline-formula> 2.13%) within the range of -20 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C to 90 <inline-formula><tex-math notation="LaTeX">$^\circ$</tex-math></inline-formula> C.

Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM

In this paper, we present a reconfigurable Physically Unclonable Functions (PUF) based on the Spin-Orbit-Torque Magnetic Random-Access Memory (SOT-MRAM), which exploits thermal noise as the true dynamic entropy source. Therefore, the MRAM cells could be configured to random final states with stochastic switching mechanism. The proposed PUF is constructed and reconfigured by combining the small-capacity true random number generator (TRNG) and high-reliability secure hash algorithm (SHA-512), realizing the dynamic transformation between SOT-MRAM based last level cache and PUF (In-Cache-MPUF). Thanks to the full reconfigurability and the high endurance of SOT-MRAM, the proposed In-Cache-MPUF can achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{\textbf {14}}$ </tex-math></inline-formula> maximum PUF bits per cell, which has greatly motivated the implementations compared with the traditional weak PUFs utilizing the static entropy source of process variations. The Monte-Carlo simulation results using 40 nm technology and a compact MTJ model show that the proposed PUF has desirable randomness as the digitized bit streams passing all the NIST tests, achieving 50.0428% uniqueness as well as 49.9236% uniformity. It also shows comparable reliability to the state-of-the-art works: a maximum bit error rate of 0.14% and 0.12% at 100 °C and 0.9 V, respectively. In addition, the system level performance is tested and validated by gem5.

CRP: Conditional Replacement Policy for Reliability Enhancement of STT-MRAM Caches

Driven by the trends of emerging technologies in on-chip memories, with increasing the size of last-level caches (LLCs), spin-transfer torque magnetic random access memories (STT-MRAMs) are the most promising alternative technology among the non-volatile memories (NVMs) to replace SRAMs. Despite their high density, scalability, and near-zero leakage power, the reliability of STT-MRAM LLCs is threatened by a high error rate due to their stochastic switching behavior. The error rate is highly influenced by the cache management, which necessitates redesigning the cache replacement policy based on the error behavior. In this article, we propose an error-aware cache replacement policy, namely, conditional replacement policy (CRP), to improve the reliability of STT-MRAM caches by decreasing the rate of both read disturbance and write failure. This is ascertained by nominating an appropriate data block in the cache to be replaced with an incoming data block, considering the minimum error rate. Moreover, the performance and latency of both write and read operations are considered. The simulation results show that compared with the state-of-the-art replacement policy in STT-MRAM caches, CRP reduces the total error rate by 68%. In addition, the proposed policy enhances the performance by 2% and saves energy consumption by 19%, on average. Meanwhile, the total number of writes is decreased by 41% compared with the previous scheme.

Electron-beam-evaporation-based multi-source oxide MBE as a synthesis method for high-quality and novel magnetic materials—beyond 3d transition metal compounds

Magnetism and magnetic materials are among the most extensively studied research topics in condensed matter physics. While many practical applications of magnetic materials have been already launched, including permanent magnet motors, magnetic heads in hard disc drives (HDDs), and magnetoresistive random access memories (MRAMs), further search for new magnetic materials has not lost its charm. Here, we show that a multi-electron gun MBE apparatus for oxides, equipped with a high precision rate control system enables the synthesis of well-known ferromagnetic oxides, e.g., SrRuO3 of unparalleled quality. Furthermore, this method also allows to fetch novel magnetic materials, e.g., Sr3OsO6, that are well outside of the synthesis conditions known from 3d transition metal oxides.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

Two-dimensional materials prospects for non-volatile spintronic memories.

Non-volatile magnetic random-access memories (MRAMs), such as spin-transfer torque MRAM and next-generation spin-orbit torque MRAM, are emerging as key to enabling low-power technologies, which are expected to spread over large markets from embedded memories to the Internet of Things. Concurrently, the development and performances of devices based on two-dimensional van der Waals heterostructures bring ultracompact multilayer compounds with unprecedented material-engineering capabilities. Here we provide an overview of the current developments and challenges in regardto MRAM, and then outline the opportunities that can arise by incorporating two-dimensional material technologies. We highlight the fundamental properties of atomically smooth interfaces, the reduced material intermixing, the crystal symmetries and the proximity effects as the key drivers for possible disruptive improvements for MRAM at advanced technology nodes.

Two-Dimensional Error Correction Code for Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) Caches

Spin-Transfer Torque Magnetic Random-Access Memory (STT-MRAM) is an emerging nonvolatile memory (NVM) technology that can replace conventional cache memory in computer systems. STT-RAM has many desirable properties such as high writing and reading speed, non-volatility, and low power consumption. Since the cache requires a high speed of writing and reading speed, a single-error correction and double error detection (SEC - DED) are applicable to improve the reliability of the cache. However, the process variation and thermal fluctuation of STT-MRAM cause errors. For example, writing ‘1’ bits has more errors than writing ‘0’ bits. We then design the weight reduction code to reduce the error caused by writing ‘1’ bits. Moreover, the performance of an SEC-DED code is improved by constructing an SED-DED code as the product code. The simulation results demonstrate that the two-dimensional error correction code consisting of product code and weight reduction code is roughly 5.67 × 10−4 lower than the SEC-DED code when the error rate of writing ‘1’ bits is equal to 6 × 10−3.

Highly efficient voltage-controlled magnetism in HfZrO/CoFeB hybrid film and Hall device

We investigate the voltage-controlled magnetism effect of HfZrO/CoFeB hybrid film and a Hall device with perpendicular magnetic anisotropy. The magnetization versus magnetic field experiments and anomalous Hall experiments before and after applying voltage are performed. The results exhibit that the coercive field of samples remain unchanged while the saturation magnetization shows a permanent increase (more than 60%), which is regardless of the direction of applied voltage. Different from conventional voltage-controlled magnetic anisotropy, in our work, only the saturation magnetization is enhanced by the applied voltage without trading off other magnetic parameters of CoFeB. Thus, such a finding proposes a more efficient voltage-controlled method to achieve a magnetic memory device with high thermal stability, high tunnel magnetoresistance and low switching current for magneto-resistive random-access memory under scaling beyond 2X nm.

Mars Exploration Using Sailplanes

We present the preliminary design of sailplanes, used for Mars exploration. The sailplanes mitigate the weight and energy storage limitations traditionally associated with powered flight by instead exploiting atmospheric wind gradients for dynamic soaring, and slope/thermal updrafts for static soaring. Equations of motion for the sailplanes were combined with wind profiles from the Mars Regional Atmospheric Modeling System (MRAMS) for two representative sites: Jezero crater, Perseverance’s landing site, and over a section of the Valles Marineris canyon. Optimal flight trajectories were obtained from the constrained optimization problem, using the lift coefficient and the roll angle as control parameters. Numerical results for complete dynamic soaring cycles demonstrated that the total sailplane energy at the end of a soaring cycle increases by 6.8–11%. The absence of a propulsion system, allowing for a compact form factor, means the sailplanes can be packaged into CubeSats and deployed as secondary payloads at a relatively low cost; providing scientific data over locations inaccessible by current landers and rovers. Various sailplane deployment methods are considered, including rapid deployment during Entry, Descent, and Landing (EDL) of a Mars Science Laboratory-class (MSL) vehicle and slow deployment using a blimp.

Electrical Properties of New Carbon-Based Magnetic Nanomaterials and Spintronic Device Design

Magnetic thin films with perpendicular anisotropy have important application value in magnetic random access memory (MRAM), track storage, spin logic and other devices, which have attracted widespread attention. Among the current common spintronic devices, CoFeB thin films and Co/Ni multilayer films have become ideal magnetic thin film materials for spintronic devices due to their large vertical anisotropy (PMA) and low damping constant. At present, the latest technology requires the thickness of the film in spintronic devices to be on the order of nanometers, which puts forward higher requirements for the preparation of magnetic films. This involves some basic issues in materials science, so the research from the perspective of materials science in the preparation process of magnetic ultra-thin films, it is particularly important to discuss the influence of preparation conditions on its microstructure and magnetic properties. This article focuses on how to obtain CoFeB films and Co/Ni multilayer films with good vertical anisotropy, and investigates the effect of the thickness of the magnetic layer in the CoFeB film, the type of substrate layer, the growth mode and the film deposition sequence on the vertical anisotropy of the CoFeB film. Influence: The influence of the substrate layer on the vertical anisotropy of the multilayer film, and the influence of the thickness and period of the magnetic layer of the multilayer film on the magnetic properties and magnetic domain structure of the Co/Ni multilayer film are studied. The physical mechanism of the change of the thickness and the number of cycles of the magnetic layer affecting the magnetic domain structure of the multilayer film is discussed. The assembled asymmetric supercapacitor has a high energy density of 36.9 Wh kg-1 (power density of 400 W kg-1) and good cycle performance (83.9% is still retained after 5000 cycles).

Modeling for Improved Performance of Ultra-Fast Nonvolatile Toggle Spin Torque MRAM Bit-Cell

In the recent past, exploiting nonvolatile memory devices to facilitate in-memory computation benchmarks has demonstrated a considerable capability to address the von-Neumann drawbacks. This process resulted in a tremendous effort towards spintronics memory development. Due to the voltage-controlled magnetic anisotropy (VCMA) effect, the toggle magnetoresistive random-access memory (MRAM) exhibits faster switching and lower power consumption than spin-transfer torque (STT) MRAM. We assessed read/write access time, magnetized time and anisotropic field for crystalline perpendicular magnetic tunnel junctions (CPMTJ) with detailed material study and device parameters in this work. These junctions are affected by the VCMA effect. Various VCMA parameters, including the VCMA coefficient, the time constant and antiparallel (AP) resistance on the saturated magnetization, are measured via the memory cell’s SPICE modeling. The Rashba spin–orbit interaction (SOI) and spin-valve model are developed by MATLAB scripting for evaluating a Rashba and Hamiltonian vector field. The toggle spin torque (TST) in the TST-MRAM cell is generated due to the interconnection between STT and spin–orbit torque (SOT) mechanisms. The TST-MRAM cell’s benefits are energy efficiency, large TMR ratio and superfast read and write operation. This work’s novel part is that the Hamiltonian field can control the net magnetization factor by the Rashba SOI effect. We end this paper with the performance enhancement techniques of MRAM cells due to VCMA and Rashba SOI effect.

SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage

Memory security has recently come into the spotlight as attackers have stepped up their efforts to gain illicit access to sensitive data or cause denial-of-memory-service via a variety of avenues like cold boot attacks, bus snooping, and physical probing or tampering. In this paper, we propose SuperVAULT, a novel secure storage solution for protecting secret data/keys by exploiting the superparamagnetic regime of nanomagnets. Through materials and dimensional engineering of the magnetic tunnel junction (MTJ) free layer, the energy barrier of spintransfer torque magnetoresistive random access memory (STTMRAM) cells can be designed to lie in the range of the thermal energy (kBT ). Such superparamagnetic MTJ (s-MTJ) cells, with an O(10 ns) retention time, need to be refreshed frequently. In the absence of data refresh (under attack conditions), the data they hold is thermally corrupted to a random state after an arbitrary but short amount of time. We leverage this property to devise a secure memory primitive and showcase its potential against cold boot and Boolean satisfiability (SAT) attacks. Further, the overheads for s-MTJ-based STT-MRAMs is shown to be promising for on-chip implementations.

A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM

This brief presents a parallel magnetoresistive random access memory (MRAM)-based strong physical unclonable function (MPUF). The proposed MPUF leverages fabrication-induced process variations of magnetic tunnel junction (MTJ) and compares the resistance of MRAM cells to obtain a 1-bit response value. Contrary to arbiter PUF, the proposed MPUF achieves maximum security by satisfying strict avalanche criterion (SAC) property, and its secrecy capacity increases linearly with CRPs. Moreover, an array selection circuit (ASC) is proposed, which injects strong non-linearity into the PUF response and improves the robustness against machine learning (ML)- based modeling attacks. The proposed MPUF demonstrates high reliability, uniqueness, and uniformity with mean intra and inter-hamming distance (HD) of 0.447% and 49.76%, respectively. The robustness evaluation of the proposed MPUF against ML attacks, such as multilayer perceptron (MLP), linear regression (LR), and support vector machine (SVM), shows that it is resistant to these attacks, with ML-attack prediction accuracy of less than 79.7% for the basic two-array MPUF and less than 53.8% for the four-array MPUF with ASC. Moreover, compared to existing PUFs, the proposed MPUF has a large CRP space, high energy efficiency, and low area occupancy.

Off-axis electron holography for the direct visualization of perpendicular shape anisotropy in nanoscale 3D magnetic random-access-memory devices

Perpendicular shape anisotropy (PSA) and double magnetic tunnel junctions (DMTJs) offer practical solutions to downscale spin-transfer-torque Magnetic Random-Access Memory (STT-MRAM) beyond 20 nm technology nodes, while retaining their thermal stability and reducing critical currents applied. However, as these modern devices become smaller and three-dimensionally (3D) complex, our understanding of their functional magnetic behavior is often indirect, relying on magnetoresistance measurements and micromagnetic modeling. In this paper, we review recent work that was performed on these structures using a range of advanced electron microscopy techniques, focusing on aspects specific to the 3D and nanoscale nature of such elements. We present the methodology for the systematic transfer of individual SST-MRAM nano-pillars from large-scale arrays to image their magnetic configurations directly using off-axis electron holography. We show that improved phase sensitivity through stacking of electron holograms can be used to image subtle variations in DMTJs and the thermal stability of &amp;lt;20 nm PSA-STT-MRAM nano-pillars during in situ heating. The experimental practicalities, benefits, and limits of using electron holography for the analysis of MRAM devices are discussed, unlocking practical pathways for direct imaging of the functional magnetic performance of these systems with high spatial resolution and sensitivity.

DDR-MRAM: Double Data Rate Magnetic RAM for Efficient Artificial Intelligence and Cache Applications

To reduce the switching delay, area overhead, and power consumption in the magnetic tunnel junction (MTJ)-based memories, this article presents a double data rate magnetic random access memory (DDR-MRAM), which can store information at both clock levels. The proposed memory structure is such that any MTJ type (perpendicular or in-plane) and any switching method can be used as needed. The post-layout simulations based on 40 nm TSMC CMOS technology show that the proposed DDR-MRAM has at least 52% lower write PDP and at least 32% less area-to-maximum input frequency ratio than the conventional MRAMs. Monte–Carlo simulations also confirm the correct and robust operation of the proposed memory in the presence of the inevitable process variation. Moreover, based on the designed DDR-MRAM cell, three architectures are proposed to design <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays. These architectures are designed and optimized for a specific application, including artificial intelligence (AI) hardware accelerators, high-capacity memory banks, and high-speed cache memories. The simulation results of the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays show that these arrays offer 100% higher data frequency and at least 28% less area-to-maximum input frequency ratio than the conventional MRAM arrays.

An Algorithm-Hardware Co-Design for Bayesian Neural Network Utilizing SOT-MRAM’s Inherent Stochasticity

Probabilistic machine learning plays a central role in the domains such as decision-making and autonomous control benefitting from its ability of representing and manipulating uncertainty about models and predictions. Until now, there are few hardware considerations to address the intensive computation and true random number generation for Bayesian neural network (BayesNN), whose weights are represented by probability distributions. In this article, we propose to apply the local reparameterization trick to alleviate the burden of random number generators (RNGs), which could be implemented by utilizing the inherent random noise of spin-orbit torque magnetic random access memory (SOT-MRAM). Sampling strategies are discussed to significantly reduce the number of operations and parameters of BayesNN. A device-circuit-system benchmark framework is then developed to evaluate the effects of device nonidealities such as the bias and variation of switching probability. The evaluation on the CIFAR-10 dataset suggests that BayesNN could achieve comparable accuracy as conventional deep neural network (DNN) with acceptable hardware overhead but provide much better uncertainty calibration with respect to out-of-distribution (OOD) inputs (rotated images as the example).

Linear Error Correction Codec Implementation Based on an In-Memory Computing Architecture for Nonvolatile Memories

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs.

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device

The development of security-aware mobile devices using wide-input–output (IO) nonvolatile memory (NVM) is hindered by high peak current, large area overhead for high read bandwidth (BWR), and considerable energy consumption for data movement between NVM and logic blocks. Furthermore, data stored in NVM are vulnerable to reverse-engineering attacks. This work presents a high BWR security-aware near-memory-computing spin-transfer torque magnetic random-access memory (STT-MRAM) macro using a multi-bit current-mode sense amplifier (MB-CSA) to reduce peak current and energy consumption for wide-IO access, a near-memory shift-and-rotate functionality (NSRF) in conjunction with the MB-CSA to reduce area overhead and enable the completion of read and logic operations within a single cycle, and a reverse-engineering-proof XOR–based memory data protector to protect data stored in NVM against reverse-engineering attacks. A 1-Mb 1024-b read STT-MRAM macro with data protector fabricated using foundry embedded 22-nm STT-MRAM. This work achieved 42.67 GB/s for BWR and 0.23 pJ/b. Inclusion of the NSRF circuit reduced area overhead by 33.3% while increasing latency by only 170 ps.

Unveiling Temperature-Dependence Mechanisms of Perpendicular Magnetic Anisotropy at Fe / MgO Interfaces

The perpendicular magnetic anisotropy (PMA) at magnetic transition metal/oxide interfaces is a key element in building out-of-plane magnetized magnetic tunnel junctions for spin-transfer-torque magnetic random access memory (STT-MRAM). Size downscaling renders magnetic properties more sensitive to thermal effects. Thus, understanding the temperature dependence of the magnetic anisotropy is crucial. In this work, we theoretically address the correlation between temperature dependence of PMA and magnetization in typical Fe/MgO-based structures. In particular, the possible mechanisms behind the experiments reporting deviations from the Callen and Callen scaling power law are analyzed. At ideal interfaces, first-principles calculations reveal (i) small high-order anisotropy constants compared to first order and (ii) enhanced exchange constants. Considering these two intrinsic effects in the atomistic simulations, the temperature-dependence of the total and layer-resolved anisotropy are found to follow the Callen and Callen scaling power law, thus ruling out an intrinsic microscopic mechanism underlying deviations from this law. Besides, two possible extrinsic macroscopic mechanisms are unveiled namely the influence of the dead layer, often present in the storage layer of STT-MRAM cells, and the spatial inhomogeneities of the interfacial magnetic anisotropy. About the first mechanism, we show that the presence of a dead layer tends to reduce the scaling exponents. In the second mechanism, increasing the percentage of inhomogeneity in the interfacial PMA is revealed to decrease the scaling exponent. These results allow us to explain the difference in scaling exponents relating anisotropy and magnetization thermal variations reported in earlier experiments. This is crucial for the understanding of the thermal stability of the storage layer magnetization in STT-MRAM applications.

Differential spin Hall MRAM based low power logic circuits and multipliers

A Multiplier is an essential component that dictates the performance of modern computing systems. However, high power dissipation of complementary metal-oxide semiconductor (CMOS) multiplier circuits has become a major concern in sub 45 nm technology nodes. Recently, emerging non-volatile memory based hybrid circuits have gained a lot of attention due to the prominent feature of negligible static power consumption. Magnetic tunnel junction (MTJ) based spin-torque memories have been used for low power applications. However, spin-transfer torque magnetic random-access memory (STT-MRAM) based hybrid CMOS/MTJ circuits exhibit higher write energy and longer incubation delay. In this work, a differential spin Hall (DSH)-MRAM cell is employed for logic and circuit applications. It stores a pair of complementary bits with low write voltage and reduced area. The variability analysis of DSH-MRAM signifies the availability of sufficient margin between different resistance states. Different types of 8 × 8 and 4 × 4 hybrid CMOS/MTJ multipliers are analyzed using DSH based adders and logic gates. The proposed multipliers consume approximately 20% less power and exhibit 19% improvement in power-delay product characteristics compared to CMOS based multipliers.