DDR-MRAM: Double Data Rate Magnetic RAM for Efficient Artificial Intelligence and Cache Applications

Abstract

To reduce the switching delay, area overhead, and power consumption in the magnetic tunnel junction (MTJ)-based memories, this article presents a double data rate magnetic random access memory (DDR-MRAM), which can store information at both clock levels. The proposed memory structure is such that any MTJ type (perpendicular or in-plane) and any switching method can be used as needed. The post-layout simulations based on 40 nm TSMC CMOS technology show that the proposed DDR-MRAM has at least 52% lower write PDP and at least 32% less area-to-maximum input frequency ratio than the conventional MRAMs. Monte–Carlo simulations also confirm the correct and robust operation of the proposed memory in the presence of the inevitable process variation. Moreover, based on the designed DDR-MRAM cell, three architectures are proposed to design <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays. These architectures are designed and optimized for a specific application, including artificial intelligence (AI) hardware accelerators, high-capacity memory banks, and high-speed cache memories. The simulation results of the proposed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$m\times n$ </tex-math></inline-formula> DDR-MRAM arrays show that these arrays offer 100% higher data frequency and at least 28% less area-to-maximum input frequency ratio than the conventional MRAM arrays.