Linear Error Correction Codec Implementation Based on an In-Memory Computing Architecture for Nonvolatile Memories

Abstract

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs.