Magnetic Random Access Memory Research Articles

Approximate MRAM: High-performance and Power-efficient Computing with MRAM Chips for Error-tolerant Applications

Approximate computing (AC) leverages the inherent error resilience and is used in many big-data applications from various domains such as multimedia, computer vision, signal processing, and machine learning to improve systems performance and power consumption. Like many other approximate circuits and algorithms, the memory subsystem can also be used to enhance performance and save power significantly. This paper proposes an efficient and effective systematic methodology to construct an approximate non-volatile magneto-resistive RAM (MRAM) framework using consumer-off-the-shelf (COTS) MRAM chips. In the proposed scheme, an extensive experimental characterization of memory errors is performed by manipulating the write latency of MRAM chips which exploits the inherent (intrinsic/extrinsic process variation) stochastic switching behavior of magnetic tunnel junctions (MTJs). The experimental results and error-resilient image application reveal that the proposed AC framework provides a significant performance improvement and demonstrates a maximum reduction in MRAM write current of ~66% on average with negligible or no loss in output quality.

Comparison of performance among five types of tunneling magnetoresistance linear sensing units based on MgO magnetic tunnel junction

Magnetic tunnel junction (MTJ) has been successfully used in spintronic devices, such as magnetoresistive random access memory, tunneling magnetoresistance (TMR) sensor, magnetic logic. In the TMR sensor a special magnetic structure is used between the free layer and the pinned layer of an MTJ to realize a linear output. So far, five types of TMR linear sensing units (TMR-LSNs) have been developed based on MgO MTJs, which are artificial-indirect-double-exchange-coupling-, magnetic-field-biased-, in-plane-, perpendicular-, and superparamagnetic-TMR-LSN, respectively. In this paper, the five types of TMR-LSNs are combed and their magnetic sensing performances are systematically compared with each other. First, the five types of TMR-LSNs each have a linear resistance response to the external magnetic field with a changeable sensitivity, a linear field range and a low frequency noise level. Second, in the five types of TMR-LSNs different magnetic structures are used to realize the same aim that is to obtain the optimized performance parameters, which is of significance for putting TMR sensors into practical applications. Third, the five types of TMR-LSNs are suitable for different application scenarios due to their respective performance parameters. Therefore, we believe that our summarized discussion in this paper will help people to explore and find the relevant applications of TMR sensors based on the five types of TMR-LSNs.

Effect of Buffer and Cap Layer on Thermally Stable Perpendicular Magnetic Anisotropy in Buffer/CoFeB/MgO/Cap Structure

The effect of buffer and cap layer on thermally stable perpendicular magnetic anisotropy (PMA) in buffer/CoFeB/MgO/cap structure was designed to detailed study. Not only the buffer layer is crucial, but the type of cap layer also affects the thermal stability of PMA. Relatively to the Ta samples, the W samples adopting W buffer or cap layer get a wider PMA thickness range for further increasing thermal stability of PMA in magnetic random access memory (MRAM) applications. And the same as the W buffer layer, the annealing temperature for W cap layer is also increased 30°C (from 270°C to 300°C). Via the detailed anomalous Hall effect (AHE) measurements, the thermal stability of PMA in buffer/CoFeB/MgO/cap was investigated. This work provides a promising way to obtain high thermal stability of PMA in CoFeB-MgO-based spintronic applications, and it is significant for designing the next-generation information storage devices.

Ionization and Displacement Damage on Nanostructure of Spin–Orbit Torque Magnetic Tunnel Junction

Spin–orbit torque magnetic tunnel junction (SOT-MTJ) is the memory cell of magnetic random access memory (MRAM), which is a promising candidate for upper level cache in the harsh environment due to nonvolatility, high speed, and high endurance. Therefore, it is significant to research the mechanism of irradiation effects on the SOT-MTJ before its integration onboard. This article investigates the ionization and displacement damage of in-plane magnetic anisotropy SOT-MTJ, including 1-MeV electron and 17.2-keV He <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co gamma irradiations with various fluences and doses, respectively. The devices are resilient to tunnel magnetoresistance (TMR), whereas the magnetic properties are changed after irradiation. The 100-Mrad (Si) gamma and 17.2-keV He <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> irradiations generate similar damages on the device performances, in the aspects of the magnetic anisotropy and critical current density ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$J_{\mathrm {c}}$ </tex-math></inline-formula> ). However, the displacement damage originating from the electron irradiation does not have a significant influence on <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$J_{\mathrm {c}}$ </tex-math></inline-formula> . In addition, the saturation magnetization and exchange bias field are changed by irradiations without regularity. Some possible mechanisms are discussed to explain the experimental results through the simulation of stopping and range of ions in matter (SRIM) and microstructural tests.

Novel Radiation Hardened SOT-MRAM Read Circuit for Multi-Node Upset Tolerance

The rapid transistor scaling and threshold voltage reduction pose several challenges such as high leakage current and reliability issues. These challenges also make VLSI circuits more susceptible to soft-errors, particularly when subjected to harsh environmental conditions. Hybrid spintronic/CMOS technology has emerged as one of the promising techniques to achieve low leakage power and non-volatility. Moreover, the spintronic memories are inherently resistant to the radiation effects such as heavy-ion irradiation and total ionizing dose. However, its CMOS peripheral circuitry is more susceptible to radiation-induced single-event upset (SEU) and double-node upset (DNU). In this paper, a new radiation-hardened read circuit for SOT magnetic random access memory (MRAM) on 45nm technology has been presented. The proposed circuit is highly resistant to all the probable SEUs and DNUs when compared to the previously reported designs. The results show that it can tolerate 4.5X, 11X, 9X, and 10.5X more critical charge as compared to the cross-coupled CMOS transistor, 11T, 13T, and 11T radiation hardened circuits, respectively. Moreover, the recovery time of the proposed circuit is improved by 20% when compared to cross-coupled CMOS transistor circuits.

Single Event Upsets Under Proton, Thermal, and Fast Neutron Irradiation in Emerging Nonvolatile Memories

In New Space, the need for reduced cost, higher performance, and more prompt delivery plans in radiation-harsh environments have motivated spacecraft designers to use Commercial-Off-The-Shelf (COTS) memories and emerging technology devices. This paper investigates the behavior of state-of-the-art memories manufactured in emerging technologies, including Ferroelectric Random-Access Memory (FRAM), Resistive Random-Access Memory (ReRAM), and Magnetic Random-Access Memory (MRAM), against radiation effects in static and dynamic modes. Radiation-ground tests were conducted under 15-MeV and 1-MeV protons, thermal and 14.8-MeV neutrons leading to various categories of radiation effects. Experimental results will show clear evidence of the robustness of bitcells manufactured using these emerging technologies against radiation, but at the same time, some susceptibility in these devices to suffer radiation effects when working in dynamic mode. Experimental results with the CY15B102Q and CY15B104Q FRAMs (Infineon Technologies), the MB85AS4MT, and MB85AS8MT ReRAMs (Fujitsu), and the MR10Q010CSC and MR25H40CDF MRAMs (Everspin) will be presented and discussed.

Spin–orbit torque driven perpendicular magnetization switching in Re/CoFeB/MgO with high thermal stability

Writing using spin–orbit torque (SOT) has been widely investigated in the field of magnetic random-access memory (MRAM). Heavy metal (HM)/CoFeB/MgO is the core of this SOT-MRAM structure. The heterostructure consisting of Ta as the spin current source and CoFeB/MgO as the perpendicular magnetic anisotropy (PMA) material is the most researched structure, owing to its high tunneling magnetoresistance ratio. However, Ta is difficult to integrate into the CMOS process due to its poor thermal stability against annealing at temperatures greater than 350 °C. Currently, β-tungsten (W) is the only HM with the CoFeB/MgO system, which can provide both thermal stability and SOT switching. Nevertheless, to achieve the high resistive β phase of W is a challenging task. Here, we report another material rhenium (Re) capable of providing thermally stable PMA up to temperature 425 °C with a perpendicular anisotropic field greater than 5000 Oe; Re possesses a spin hall angle (ϴSH) of 0.065 ± 0.003, and SOT switching can be achieved with a current density around 1.36 × 1011 A/m2. Our findings pave a new avenue for the material design of perpendicular SOT-based MRAM.

Process-Induced Magnetic Tunnel Junction Damage and its Recovery for the Development of Spin-Orbit Torque Magnetic Random Access Memory

Process-Induced Magnetic Tunnel Junction Damage and its Recovery for the Development of Spin-Orbit Torque Magnetic Random Access Memory

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14&#x0025; on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8&#x0025; higher than the baseline when PROI is applied with PIDE and NPW.

A Novel Workload-Aware and Optimized Write Cycles in NVRAM

With the emergence of the Internet of things (IoT), embedded systems have now changed its dimensionality and it is applied in various domains such as healthcare, home automation and mainly Industry 4.0. These Embedded IoT devices are mostly battery-driven. It has been analyzed that usage of Dynamic Random-Access Memory (DRAM) centered core memory is considered the most significant source of high energy utility in Embedded IoT devices. For achieving the low power consumption in these devices, Non-volatile memory (NVM) devices such as Parameter Random Access Memory (PRAM) and Spin-Transfer Torque Magnetic Random-Access Memory (STT-RAM) are becoming popular among main memory alternatives in embedded IoT devices because of their features such as high thickness, byte addressability, high scalability and low power intake. Additionally, Non-volatile Random-Access Memory (NVRAM) is widely adopted to save the data in the embedded IoT devices. NVM, flash memories have a limited lifetime, so it is mandatory to adopt intelligent optimization in managing the NVRAM-based embedded devices using an intelligent controller while considering the endurance issue. To address this challenge, the paper proposes a powerful, lightweight machine learning-based workload-adaptive write schemes of the NVRAM, which can increase the lifetime and reduce the energy consumption of the processors. The proposed system consists of three phases like Workload Characterization, Intelligent Compression and Memory Allocators. These phases are used for distributing the write-cycles to NVRAM, following the energy-time consumption and number of data bytes. The extensive experimentations are carried out using the IoMT (Internet of Medical things) benchmark in which the different endurance factors such as application delay, energy and write-time factors were evaluated and compared with the different existing algorithms.

Micromagnetic simulation of vortex core polarity in bi-component magnetic nanodisks

The nucleation and management of the vortex state in magnetic nanostructures has received a lot of interest in recent decades, with potential applications in logic networks and non-volatile magnetic random-access memory. Because of their potential use in magnetic memory, magnetic vortex structures are of considerable technical importance. Investigation of bi-component magnetic nanodisks as prospective storage systems, in both single and coupled configurations, has been performed, where the information unit is represented by vortex core polarity. The work mainly engages in magnetic nanodisks of permalloy and iron having a diameter of 200 nm and a thickness of 40 nm. The potential of adjusting the polarity of the vortex core by the application of a magnetic field using micromagnetic simulations has been illustrated. Micromagnetic simulation studies show that bi-material structures are important not just for fundamental research but also for data storage.

Design of a STT-MTJ Based Random-Access Memory With In-situ Processing for Data-Intensive Applications

During the last few years, deep learning techniques are frequently applied in large-scale image processing, detection in a variety of computer vision, cognitive tasks, and information analysis applications. The execution of deep learning algorithms like CNN and FCNN requires high dimensional matrix multiplication, which contributes to significant computational power. The frequent data movement between memory and core is one of the main reasons for considerable power consumption and latency, hence becoming a major performance bottleneck for conventional computing systems. To address this challenge, we propose an in-memory computing array that can perform computation directly within the memory, hence, reducing the overhead associated with data movement. The proposed Random-Access Memory with in-situ Processing (RAMP) array reconfigures the emerging magnetic random-access memory to realize logic and arithmetic functions inside the memory. Furthermore, the array supports independent operations over multiple rows and columns, which helps in accelerating the execution of matrix operations. To validate the functionality and evaluate the performance of the proposed array, we perform extensive spice simulations. At 45nm, the proposed array takes 5.39 ns, 0.68 ns, 0.68 ns, 0.7 ns and consumes 2.2 pJ&#x002F;bit, 0.21 pJ&#x002F;bit, 0.23 pJ&#x002F;bit, 0.7 pJ&#x002F;bit while performing a memory write, memory read, logic, and arithmetic operations respectively.

Probing the Spin Hall Characteristics of W/CoFeB/MgO Based Heterostructures for Spin‐Orbit Torque Based Magnetic Random Access Memory Application

AbstractIn this work, the spin Hall characteristics of W/CoFeB/MgO have been systematically studied to provide an in‐depth insight for the optimization of the SOT‐MRAM channel. The bcc and β phases of tungsten (W) are identified clearly from XRD and resistivity studies, which shows marked impact on the electrical characteristics. Moreover, the same is found have tremendous affect on W's spin Hall characteristics with a twelvefold increase of the spin Hall angle ΘSH. The evaluation of W/CoFeB interfacial spin mixing conductance using ab initio studies shows good coherency with the same evaluated experimentally, which is used to estimate interfacial spin transparency T&lt;/&gt; to accurately evaluate intrinsic spin Hall conductivity σSH of W. The findings equivocate for a strong claim on β‐W's σSH to be around −0.23 ∓ 0.03, addressing the ongoing discrepancy. Increasing boron concentration in (Co1Fe3)100−xBx and thermal annealing temperature are found to reduce ΘSH effectively which is inferred to boron diffusion toward W. Alloying of W with Ta does not necessarily enhance ΘSH, for which very optimized relative concentration and the alloy growth phase is critical. The findings can significantly contribute to the ongoing SOT‐MRAM development for achieving various means of control for improvement in the device characteristics.

Probability Distribution of the Write-Error Rate of Voltage-Controlled Magnetoresistive Random-Access Memories

In this study, we theoretically explore the probability distribution of the write-error rate (WER) of a voltage-controlled magnetoresistive random-access memory (VC MRAM). A probability density function (PDF) of the WER is analytically obtained using the change-of-variable technique with the assumption that the anisotropy constant of the VC MRAM follows the normal distribution. Furthermore, we assume that the WER of a single memory cell forms a parabola as a function of the anisotropy constant, resulting from numerical simulations by solving the Landau-Lifshitz-Gilbert equation based on the macrospin model. Theoretical analysis facilitates in identifying types of the PDF: a monotonic decreasing function with a peak at the smallest WER, and a function with local maximum.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Perpendicular magnetic tunnel junctions with multi-interface free layer

Future generations of magnetic random access memory demand magnetic tunnel junctions that can provide simultaneously high magnetoresistance, strong retention, low switching energy, and small cell size below 10 nm. Here, we study perpendicular magnetic tunnel junctions with composite free layers, where multiple ferromagnet/nonmagnet interfaces can contribute to the thermal stability. Different nonmagnetic materials (MgO, Ta, and Mo) have been employed as the coupling layers in these multi-interface free layers. The evolution of junction properties under different annealing conditions is investigated. A strong dependence of the tunneling magnetoresistance on the thickness of the first CoFeB layer has been observed. In junctions where Mo and MgO are used as coupling layers, a large tunneling magnetoresistance above 200% has been achieved after 400 °C annealing.

Optimization of Tungsten β -Phase Window for Spin-Orbit-Torque Magnetic Random-Access Memory

Switching induced by spin-orbit torque (SOT) is being vigorously explored, as it allows the control of magnetization using an in-plane current, which enables a three-terminal magnetic-tunnel-junction geometry with isolated read and write paths. This significantly improves the device endurance and the read stability, and allows reliable subnanosecond switching. Tungsten in the $\ensuremath{\beta}$ phase, $\ensuremath{\beta}$-$\mathrm{W}$, has the largest reported antidamping SOT charge-to-spin conversion ratio $({\ensuremath{\theta}}_{\mathrm{AD}}\ensuremath{\approx}\ensuremath{-}60\mathrm{%})$ for heavy metals. However, $\ensuremath{\beta}$-$\mathrm{W}$ has a limitation when one is aiming for reliable technology integration: the $\ensuremath{\beta}$ phase is limited to a thickness of a few nanometers and enters the $\ensuremath{\alpha}$ phase above 4 nm in our samples when industry-relevant deposition tools are used. Here, we report our approach to extending the range of $\ensuremath{\beta}$-$\mathrm{W}$, while simultaneously improving the SOT efficiency by introducing $\mathrm{N}$ and $\mathrm{O}$ doping of $\mathrm{W}$. Resistivity and XRD measurements confirm the extension of the $\ensuremath{\beta}$ phase from 4 nm to more than 10 nm, and transport characterization shows an effective SOT efficiency larger than $\ensuremath{-}44.4\mathrm{%}$ (reaching approximately $\ensuremath{-}60\mathrm{%}$ for the bulk contribution). In addition, we demonstrate the possibility of controlling and enhancing the perpendicular magnetic anisotropy of a storage layer ($\mathrm{Co}\text{\ensuremath{-}}\mathrm{Fe}\text{\ensuremath{-}}\mathrm{B}$). Further, we integrate the optimized $\mathrm{W}(\mathrm{O},\mathrm{N})$ into SOT magnetic random-access memory (SOT-MRAM) devices and project that, for the same thickness of SOT material, the switching current decreases by 25% in optimized $\mathrm{W}(\mathrm{O},\mathrm{N})$ compared with our standard $\mathrm{W}$. Our results open the path to using and further optimizing $\mathrm{W}$ for integration of SOT-MRAM technology.

Write Asymmetry of Spin-Orbit Torque Memory Induced by in-Plane Magnetic Fields

Write asymmetry, the significantly different write current for high-to-low and low-to-high resistance switching because of natural stochastic behaviors of magnetization, is a fundamental issue in magnetic random-access memory (MRAM). For high-performance spin transfer torque (STT) MRAM, it can be eliminated by precisely controlling atomically thin magnetic multilayers or by introducing compensation techniques in circuit-level designs, while for spin-orbit torque (SOT) MRAM, it has not been addressed. Here we systematically investigated the write asymmetry of SOT-MRAM as a function of applied magnetic fields (H) and demonstrated that the write currents are intrinsically asymmetric due to different SOT efficiencies for high-to-low and low-to-high switching. Furthermore, we found that the SOT efficiency is very sensitive to the tilt angle between H and write current, which can be tuned through H to achieve symmetric SOT switching. These results provide an additional guideline for designing SOT devices and suggest that the write asymmetry can be eliminated by adjusting the introduced effective magnetic fields within a field-free SOT-MRAM architecture.

High-Accuracy Deep Belief Network: Fuzzy Neural Networks Using MRAM-Based Stochastic Neurons

Two-terminal magnetoresistive random access memory (MRAM) devices provide a recent approach to intrinsically realizing stochastic neuronal behavior in cognitive architectures such as restricted Boltzmann machines (RBMs) for deep belief networks (DBNs). MRAM-based DBNs have achieved substantial energy and area improvements in comparison with the prior DBN hardware implementations. However, MRAM-based DBNs suffer from low accuracy in image classification. In order to resolve this problem, we present a new DBN-fuzzy system based on the combination of MRAM-based DBNs and fuzzy systems in the interest of improving the accuracy of MRAM-based neural networks. First, the MRAM-based DBN is employed to identify the top recognition results with the highest probability. Second, the fuzzy system is utilized to obtain the top-1 recognition results. We assess the accuracy of neural networks on the MNIST dataset, finding that the top-1 accuracy of the DBN-fuzzy neural network is improved from 64% to 82% in comparison to the MRAM-based DBNs for a $784\times10$ network.

A Fokker–Planck Approach for Modeling the Stochastic Phenomena in Magnetic and Resistive Random Access Memory Devices

Embedded non-volatile memory technologies such as resistive random access memory (RRAM) and spin-transfer torque magnetic RAM (STT MRAM) are increasingly being researched for application in neuromorphic computing and hardware accelerators for AI. However, the stochastic write processes in these memory technologies affect their yield and need to be studied alongside process variations, which drastically increase the complexity of yield analysis using the Monte Carlo approach. Therefore, we propose an approach based on the Fokker-Planck equation for modeling the stochastic write processes in STT MRAM and RRAM devices. Moreover, we show that our proposed approach can reproduce the experimental results for both STT-MRAM and RRAM devices.