LVDS Driver Research Articles

An Event-Based Neural Compressive Telemetry With >11× Loss-Less Data Reduction for High-Bandwidth Intracortical Brain Computer Interfaces.

Intracortical brain-computer interfaces offer superior spatial and temporal resolutions, but face challenges as the increasing number of recording channels introduces high amounts of data to be transferred. This requires power-hungry data serialization and telemetry, leading to potential tissue damage risks. To address this challenge, this paper introduces an event-based neural compressive telemetry (NCT) consisting of 8 channel-rotating Δ-ADCs, an event-driven serializer supporting a proposed ternary address event representation protocol, and an event-based LVDS driver. Leveraging a high sparsity of extracellular spikes and high spatial correlation of the high-density recordings, the proposed NCT achieves a compression ratio of >11.4×, while consumes only 1 µW per channel, which is 127× more efficient than state of the art. The NCT well preserves the spike waveform fidelity, and has a low normalized RMS error <23% even with a spike amplitude down to only 31 µV.

Design and evaluation of EMPIX2, a 100 kfps, high dynamic range pixel detector readout ASIC for electron microscopy

EMPIX2 is a novel hybrid pixel detector readout ASIC for electron microscopy with a maximum frame rate of 100 kfps and a very large dynamic range (5 × 105:1). It features 128 × 128 square pixels at a pitch of 150 μm. Adaptive gain switching and charge pump technology are applied to enhance the dynamic range. The pixels can operate in two modes: pulse mode and continuous mode. In pulse mode, ultra-fast gain switching enables a rapid response to pulsed electron sources, making it highly suitable for UEM applications. In continuous mode, the power consumption and dynamic range are optimized for STEM applications. The readout is frame-based, and digital image data is output by 64 pairs of LVDS drivers working in DDR mode at a clock frequency of 400 MHz. A dedicated data acquisition system was developed for the transmission and processing of the image data. Preliminary verification of the readout chip was performed using an on-chip calibration source.

Design and characterization of the FAST chip: a front-end for 4D tracking systems based on Ultra-Fast Silicon Detectors aiming at 30 ps time resolution

Detectors able to measure the time of flight with very high accuracy (∼10 ps RMS) are becoming fundamental in the design of new High Energy Physics experiments, where accurate time measurements will be used to mitigate pileup effects. The development of such detectors has spurred intense R&D in both silicon sensors and the associated readout electronics, aiming at obtaining silicon-based detectors with a time resolution in the few tens-of-picosecond range. This work presents FAST, a family of three different 20 channel amplifier-comparator chips, tailored to the readout of Ultra Fast Silicon Detectors. These ASICs have been designed optimizing the sensor-readout interplay with the aim of reaching the smallest possible jitter term. The three chips of the FAST family differ in the architecture of the front-end while sharing the channel back-end, consisting of a leading-edge discriminator and a LVDS driver. The goal of these front-ends is to achieve a time resolution of about 30 ps RMS while coupled to a sensor with a few pico-Farad capacitance, keeping the power budget of the single channel below 1.3 mW. This paper reports the description of the FAST design architecture and summarizes the results on the initial characterization of one chip of the FAST family, in a stand-alone test structure and when coupled to a UFSD.

SliT: A Strip-Sensor Readout Chip With Subnanosecond Time Walk for the J-PARC Muon g − 2/EDM Experiment

A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, which consists of a CR-RC filter followed by a CR circuit as a voltage differentiator. This architecture enables to generate hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between 0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$ (rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other functionalities such as a strip-sensor readout chip have also been proven in the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM experiment.

A high speed BiCMOS comparator ASIC with voltage adjustable hysteresis

A design of high-speed comparator ASIC, fabricated in 0.35μm SiGe BiCMOS process is presented. This ASIC is designed as a part of the front-end readout electronics development for Resistive Plate Chamber detector of Iron Calorimeter experiment of India based Neutrino Observatory. The ASIC comprises eight channels of high-speed voltage comparator with LVDS driver. A novel technique is used to implement a small voltage adjustable hysteresis in the comparator without additional power, area and circuit complexity. This ASIC multiplexes input analog signals through an on-chip high-speed 50 Ω cable driver. The analog multiplexer supports daisy and non-daisy modes for access of input signals. The ASIC has power consumption of ∼ 13 mW/channel. The comparator LVDS output rise time is ∼ 900 ps. The measured timing precision of the ASIC is ∼ 40 ps RMS.

Integrated front-end electronics for single photon time-stamping in cryogenic dark matter detectors

ALCOR is a first prototype of a 32-pixel low-power mixed-signal ASIC developed to readout silicon photomultipliers at low temperature. The chip, designed in 110 nm CMOS technology, performs single photon time-stamping with a maximum event rate of 5 MHz per pixel. The time measurement is performed using low-power TDCs based on analogue time interpolation. The time binning achievable at maximum clock frequency is 50 ps and the target power consumption is less than 5 mW per pixel. Generated data are serialised and transmitted through LVDS drivers. To assert the CMOS electronic behaviour at 77 K, a Test Chip has been produced and tested. Results of a digital synchronisation circuit are reported and discussed.

MALTA: an asynchronous readout CMOS monolithic pixel detector for the ATLAS High-Luminosity upgrade

The ATLAS collaboration is currently investigating CMOS monolithic pixel sensors for the outermost layer of the upgrade of its Inner Tracker (ITk). For this application, two large scale prototypes featuring small collection electrode have been produced in a radiation-hard process modification of a standard 0.18 μm CMOS imaging technology: the MALTA, with a novel asynchronous readout, and the TJ MONOPIX, based on the well established “column-drain” architecture. The MALTA chip is the first full-scale prototype suitable for the development of a monolithic module for the ITk. It features a fast and low-power front-end, an architecture designed to cope with an hit-rate up to 2 MHz/mm2 without clock distribution over the matrix, hence reducing total power consumption, and LVDS drivers. Laboratory tests confirmed the performance of the asynchronous architecture expected from simulations. Extensive testbeam measurements have proved an average detection efficiency of 96% before irradiation at a threshold of ∼230 e− with dispersion of ∼36 e− and ENC lower than 10 e−. A non fully functional pixel masking scheme, forces operation at relatively high thresholds, causing inefficiency. A severe degradation of efficiency has been measured after neutron irradiation at a fluence 1 × 1015 1 MeV neq/cm2. Consistent results have been produced with the TJ MONOPIX. A correlation with inefficiency plots and pixel layout has triggered TCAD simulations, ending up to two possible solutions, implemented in a new prototype, the MiniMALTA.

Design of a power efficient self-adaptive LVDS driver

Design of a power efficient self-adaptive LVDS driver

A 128-ch Δ-Σ ADC based mixed signal IC for full digital beamforming Wireless handheld Ultrasound imaging system.

This paper reports a massively integrated Δ-Σ ADC based mixed signal chipset for a handheld Wireless Ultrasound imaging system. The IC has been fabricated in a standard 0.13 μm 1.5V 7M2F CMOS process with 128 parallel channels containing Delta-Sigma (Δ-Σ) ADCs, Anti-aliasing filter, Decimation filters, Serializers and LVDS drivers. The entire chip is SPI controlled and allows group-level power control through an FPGA. The IC measures 15 × 15 mm and dissipates around ~ 4.6 W of power, with 12-bit resolution at 20 Msps sample rate. The chip was packaged in a thermally stable BGA package and demonstrated in a handheld ultrasound battery operated system with complete digital beamforming.

A 10 MS/s 8-bit charge-redistribution ADC for hybrid pixel applications in 65 m CMOS

The design and measurement results of an 8-bit SAR ADC, based on a charge-redistribution DAC, are presented. This ADC is characterized by superior power efficiency and small area, realized by employing a lateral metal–metal capacitor array and a dynamic two-stage comparator. To avoid the need for a high-speed clock and its associated power consumption, an asynchronous logic was implemented in a logic control cell. A test chip has been developed in a 65nm CMOS technology, including eight ADC channels with different layout flavors of the capacitor array, a transimpedance amplifier as a signal input structure, a serializer, and a custom-made LVDS driver for data transmission. The integral (INL) and differential (DNL) nonlinearities are measured below 0.5 LSB and 0.8 LSB, respectively, for the best channel operating at a sampling frequency of 10 MS/s. The area occupies 40μm×70μm for one ADC channel. The power consumption is estimated as 4μW at 1MS/s and 38μW at 10MS/s with a supply rail of 1.2V. These excellent performance features and the natural radiation hardness of the design, due to the thin gate oxide thickness of transistors, are very interesting for front-end electronics ICs of future hybrid-pixel detector systems.

Prompt trigger primitives for a self-seeded track trigger

A viable self-seeded track trigger for a high rate collider detector environment must have excellent angular precision, response times commensurate with beam crossing rate and low mass. We have designed a fast clustering block servicing 128 contiguous strips to be included in an LHC upgrade silicon strip front end ASIC (ABC130) with these objectives in mind. The block is based on the presence of an analog front end with binary (threshold determined) strip readout latched at each beam crossing. Combinatorial logic tests for the presence of one or two adjacent strips over threshold, a qualifying cluster, at each beam crossing and transmits up to two, eight bits clusters descriptors, specifying address and cluster width via a high speed LVDS output. It is envisioned that a correlator chip, presently in conception, receives this data and via look-up tables checks for coincident hits between silicon strip layers. Since the clustering output will report the presence of one or two hit strips, a half strip pitch ( ∼ 40 um for the ATLAS detector) resolution may be possible for each cluster. Our timing results show that the combinatorial clustering logic will settle within 6 ns. Assuming a beam crossing rate of 40 MHz, 16 bits of serialized data can be shifted out at 640MHz each crossing. This will allow a beam synchronous update rate providing data for up to two clusters for each bank of 128 strips. The data latency into the correlator chip will be only two crossings.Present power estimates suggest that the fast cluster block with LVDS driver will consume less than 12 mW.

Cryogenic digital data links for the liquid argon time projection chamber

In this paper we present the cryogenic functionality of the components of data links for the Liquid Argon Time Projection Chamber (LArTPC), a potential far site detector technology of the Long-Baseline Neutrino Experiment (LBNE). We have confirmed that an LVDS driver can drive a 20-meter CAT5E twisted pair up to 1 gigabit per second at the liquid nitrogen temperature (77 K). We have verified that a commercial-off-the-shelf (COTS) serializer, a laser diode driver, laser diodes, optical fibers and connectors, and field-programming gate arrays (FPGA`s) continue to function at 77 K. A variety of COTS resistors and capacitors have been tested at 77 K. All tests we have conducted show that the cryogenic digital data links for the liquid argon time projection chamber are promising.

The Cryogenic Performances of Specific Optical and Electrical Components for a Liquid Argon Time Projection Chamber

In this paper we present a cryogenic performance study of specific optical and electrical components for the Liquid Argon Time Projection Chamber (LArTPC), a potential far site detector technology of the long baseline neutrino experiment (LBNE). We have confirmed that an LVDS driver can drive a 20-meter CAT5E twisted pair up to 1 gigabit per second at liquid nitrogen temperature (77 K). We have verified that a 16:1 serializer Application Specific Integrated Circuit (ASIC), three types of laser diodes, optical fibers and connectors, and field-programming gate arrays (FPGAs) continue to function at 77 K. A variety of commercial resistors and capacitors have been tested at 77 K. All tests we have conducted show that the cold front-end electronics is promising.

A Single-Chip 8-Band CMOS Transceiver for 3G Cellular Systems with Digital Interface

In this paper, a single-chip dual-mode 8-band 130nm CMOS transceiver including A/D/A converters and digital filters with 312MHz LVDS interface is presented. For a transmitter chain, linear direct quadrature modulation architecture is introduced for both W-CDMA/HSDPA (High Speed Uplink Packet Access) and for GSM/EDGE. Analog baseband LPFs and quadrature modulators are commonly used both for GSM and for EDGE. For a direct conversion receiver chain, ABB (Analog Base-Band) blocks, i.e., LPFs and VGAs, delta-sigma A/D converters, and FIR filters are commonly used for W-CDMA/HSDPA (High Speed Downlink Packet Access) and GSM/EDGE to reduce chip area. Their characteristics can be reconfigured by register-based control sequence. The receiver chain also includes high-speed DC offset cancellers both in analog and in digital stage, and the self-contained AGC controller, whose parameters such as time constant are programmable to be free from DBB (Digital Base-Band) control. The transceiver also includes wide-range VCOs and fractional PLLs, an LVDS driver and receiver for high-speed digital interface of 312MHz. Measured results reveal that the transceiver satisfies 3GPP specifications for W-CDMA/HSPA (High Speed Packet Access) and GSM/EDGE.

A Distortion-Free General Purpose LVDS Driver

A general-purpose multi-Gbps LVDS driver is presented with a new distortion-free level conversion scheme. For high-speed transmission, a dynamic pre-emphasis scheme is also proposed with overdriving current effectively distributed in time. The proposed LVDS driver achieves supply-insensitive duty preservation with a reduction of switching noise by 50-percent.

Low-voltage low-power LVDS drivers

Two low-voltage low-power LVDS drivers used for high-speed point-to-point links are discussed. While the previously reported LVDS drivers cannot operate with low-voltage supplies, the proposed double current sources (DCS) LVDS driver and the switchable current sources (SCS) LVDS driver are suitable for low-voltage applications. Although static current consumption is greater than the minimum amount required by the signal swing, the DCS LVDS driver is simple and fast. The SCS LVDS driver, by dynamically switching the current sources, draws minimum static current and reduces the power consumption by 60% compared to previously reported realizations. Both drivers were fabricated in a standard 0.35-/spl mu/m CMOS process; they are compliant with LVDS standards and can operate at data rates up to gigabits-per-second.

A 1.8-V 1.6-GSample/s 8-b self-calibrating folding ADC with 7.26 ENOB at Nyquist frequency

This study demonstrates for the first time the significant performance enhancement that calibration brings to folding-interpolating analog-to-digital converters (ADCs). The resulting 1.8-V ADC in 0.18-/spl mu/m CMOS achieves a conversion rate exceeding 1.6 GSample/s, since the amplifier device sizes can be minimized to maximize speed without the restriction of device matching. At 1.6 GS/s, the ADC achieves 0.15 LSB DNL, 0.35 LSB INL, 7.6 effective number of bits (ENOBs) at 100 MHz input, and 7.26 ENOB at Nyquist. At this speed, current consumption from a single 1.8-V supply is 245 mA analog, 185 mA digital, and 90 mA for the LVDS drivers. The ac performance is approximately 1.5 ENOBs higher compared to the same circuit with calibration disabled. The use of best design practices to optimize the ADC linearity prior to introducing calibration resulted in this small required dynamic calibration range, simplifying the calibrator circuitry and resulting in stable continuous performance over time without recalibration. Therefore, the fully on-chip calibration is performed automatically, just one time at power-up.

Development of the CARIOCA front-end chip for the LHCb muon detector

CERN and Rio Current-mode Amplifier is an amplifier–shaper–discriminator chip, developed in 0.25μm CMOS radiation tolerant technology for the readout of the LHCb muon wire chambers.This paper presents the design and test of three prototype chips, including positive and negative pre-amplifier, differential shaper, differential discriminator and LVDS driver circuits.