MALTA: an asynchronous readout CMOS monolithic pixel detector for the ATLAS High-Luminosity upgrade

R Cardella,B Hiti,V Dao,H Pernegger,F Piro,A Sharma,T Wang,E J Schioppa,F Dachs,L Simon Argemi,T Hirono,N Wermes,T Hemperek,T Kugathasan,P Riedler,Leyre Flores Sanz De Acedo ,I Asensi Tortajada ,I Berdalovic,C Bespin,Carlos Solans Sánchez ,C A Marin Tobon ,W Snoeys,Konstantinos Moustakas

doi:10.1088/1748-0221/14/06/c06019

Abstract

The ATLAS collaboration is currently investigating CMOS monolithic pixel sensors for the outermost layer of the upgrade of its Inner Tracker (ITk). For this application, two large scale prototypes featuring small collection electrode have been produced in a radiation-hard process modification of a standard 0.18 μm CMOS imaging technology: the MALTA, with a novel asynchronous readout, and the TJ MONOPIX, based on the well established “column-drain” architecture. The MALTA chip is the first full-scale prototype suitable for the development of a monolithic module for the ITk. It features a fast and low-power front-end, an architecture designed to cope with an hit-rate up to 2 MHz/mm2 without clock distribution over the matrix, hence reducing total power consumption, and LVDS drivers. Laboratory tests confirmed the performance of the asynchronous architecture expected from simulations. Extensive testbeam measurements have proved an average detection efficiency of 96% before irradiation at a threshold of ∼230 e− with dispersion of ∼36 e− and ENC lower than 10 e−. A non fully functional pixel masking scheme, forces operation at relatively high thresholds, causing inefficiency. A severe degradation of efficiency has been measured after neutron irradiation at a fluence 1 × 1015 1 MeV neq/cm2. Consistent results have been produced with the TJ MONOPIX. A correlation with inefficiency plots and pixel layout has triggered TCAD simulations, ending up to two possible solutions, implemented in a new prototype, the MiniMALTA.

Highlights

: The ATLAS collaboration is currently investigating CMOS monolithic pixel sensors for the outermost layer of the upgrade of its Inner Tracker (ITk)
Two large scale prototypes featuring small collection electrode have been produced in a radiation-hard process modification of a standard 0.18 μm CMOS imaging technology: the MALTA, with a novel asynchronous readout, and the TJ MONOPIX, based on the well established “column-drain” architecture
MALTA chip is the first full-scale prototype suitable for the development of a monolithic module for the ITk. It features a fast and low-power front-end, an architecture designed to cope with an hit-rate up to 2 MHz/mm2 without clock distribution over the matrix, reducing total power consumption, and LVDS drivers

Summary

The MALTA asynchronous readout architecture

The pixels are organized in groups of 2 × 8. Hits from a pixel are sent to dedicated logic, common within the group, generating a reference pulse with a programmable width of 0.5 ns, 1 ns or 2 ns. Starting from this pulse, pixel (16 bit) and group address (5 bit) are produced. The transmission lines for the busses along the column are carefully designed to balance the load and achieve a well-defined delay from each pixel to the output. At the end of the double-column, the two busses are merged in a single bus of 22+1 bits. Two possible solutions are implemented to merge signals at the end of the double-column: a priority arbitration stage, which delays pulses arriving simultaneously, and a simple OR structure. The chip can output its data on a 40-bit wide parallel LVDS output at the bottom of the chip [12], or to one of 4 40-bit wide parallel CMOS transceivers at the left and right edge of the chip

Power consumption

Asynchronous architecture performance

Detection efficiency before and after irradiation and next steps

Steps towards system integration

Findings

Conclusions