Abstract
A new silicon-strip readout chip named "SliT" has been developed for the measurement of the muon anomalous magnetic moment and electric dipole moment at J-PARC. The SliT is designed in the Silterra 180 nm CMOS technology with mixed-signal integrated circuits. An analog circuit incorporates a conventional charge-sensitive amplifier, shaping amplifiers, and two distinct discriminators for each of 128 identical channels. A digital part includes storage memories, an event building block, a serializer, and LVDS drivers. A distinct feature of the SliT is utilization of the zero-cross architecture, which consists of a CR-RC filter followed by a CR circuit as a voltage differentiator. This architecture enables to generate hit signals with subnanosecond amplitude-independent time walk, which is the primary requirement for the experiment. The test results show the time walk of $0.38 \pm 0.16$ ns between 0.5 and 3 MIP signals. The equivalent noise charge is $1547 \pm 75 $ $e^{-}$ (rms) at $C_{\rm det} = 33$ pF as a strip-sensor capacitance. Other functionalities such as a strip-sensor readout chip have also been proven in the tests. The SliT128C satisfies all requirements of the J-PARC muon $g-2$/EDM experiment.
Highlights
T HE anomalous magnetic moment (g − 2) and the electric dipole moment (EDM) of the muon are sensitive probes of new physics beyond the Standard Model (SM)
The SM is a well-tested physics theory; there exists a discrepancy in the muon g − 2 between the SM prediction [1], [2] and its most precise measurement by the E821 collaboration at Brookhaven National Laboratory (BNL) by more than three standard deviations [3]
We have developed a series of silicon-strip readout chips named SliT with the 180-nm CMOS technology
Summary
T HE anomalous magnetic moment (g − 2) and the electric dipole moment (EDM) of the muon are sensitive probes of new physics beyond the Standard Model (SM). For the further reduction of the pileups and precise detection of circular positron tracks from the muon decays, a subnanosecond time walk is of critical importance in analog processing blocks of the readout ASIC. The sensor capacitance is approximately 17 pF, and the total detector capacitance Cdet seen from an input of the ASIC is estimated to be less than 30 pF This value includes the parasitic capacitance coming from flexible printed circuits (FPCs) [7], which connect strip sensors with ASICs. Since the maximum wiring length inside the FPCs is about 250 mm, the parasitic capacitance from the FPCs is not negligible. The module-prototype ASICs included 128 readout channels, buffer memories, and other digital processing circuits to store and cope with timing information from the strip sensors. A new readout chip named “SliT128C” improves the overall analog performance, for example, the ENC, time walk, and jitter, by optimizing transistor parameters of bias circuits in SliT128B. To suppress the digital cross talks, the analog and digital blocks are enclosed in distinct deep N-well islands
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