Memory LSI Research Articles

Channel length dependence of field-effect mobility of c-axis-aligned crystalline In–Ga–Zn–O field-effect transistors

Field-effect transistors (FETs) with c-axis-aligned crystalline In–Ga–Zn–O (CAAC-IGZO) active layers have extremely low off-state leakage current. Exploiting this feature, we investigated the application of CAAC-IGZO FETs to LSI memories. A high on-state current is required for the high-speed operation of these LSI memories. The field-effect mobility μFE of a CAAC-IGZO FET is relatively low compared with the electron mobility of single-crystal Si (sc-Si). In this study, we measured and calculated the channel length L dependence of μFE for CAAC-IGZO and sc-Si FETs. For CAAC-IGZO FETs, μFE remains almost constant, particularly when L is longer than 0.3 µm, whereas that of sc-Si FETs decreases markedly as L shortens. Thus, the μFE difference between both FET types is reduced by miniaturization. This difference in μFE behavior is attributed to the different susceptibilities of electrons to phonon scattering. On the basis of this result and the extremely low off-state leakage current of CAAC-IGZO FETs, we expect high-speed LSI memories with low power consumption.

The sprint process of Al interconnects with low-temperature PVD via filling

For multilevel interconnects of LSI memory devices, the Al sprint process using the two-step cold/hot Al PVD at less than 400°C is a realistic solution to reduction of the process cost. The process windows of via filling were investigated for via holes of 0.22µm to 0.16µm. Based on the assumption that Al diffusion decides filling capability, temperature and thickness of the cold Al liner PVD and deposition time of the hot Al PVD were optimized, resulting in complete filling of 0.16µm via holes. We have confirmed the viability of the Al PVD via filling for less than 110nm device generations.

Development of Dishing-less Slurry for Polysilicon Chemical-Mechanical Polishing Process

Dishing of polysilicon and thinning of the stopper silicon nitride films are crucial problems when the polysilicon embedded by low pressure chemical vapor deposition in the trench and the concavity with respective widths of 0.7 µm and 20–100 µm is simultaneously flattened by chemical-mechanical polishing (CMP). In order to suppress these two occurrences, a high polymer compound mixed slurry was developed and characterized. The pH value of the slurry measured on the polishing abrasive pad was decreased by dilution with de-ionized water, which resulted in cohesion and solidification of the slurry. By using this cohered and solidified slurry when the poly silicon surface is flattened by CMP, the dishing thickness of the polysilicon was suppressed to less than 100 nm at a concavity width of 100 µm. The CMP process using the developed slurry is useful for the advanced trench isolation process and is currently applied to NAND flash memory and high-speed bipolar LSI devices.

A system LSI memory redundancy technique using an ie-flash (inverse-gate-electrode flash) programming circuit

A new memory redundancy technique using inverse-gate-electrode flash (ie-flash) memory cells has been developed. The ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary in using it in system LSIs, and it can be programmed by logic testers. We enhanced the reliability of ie-flash by using some circuits, increasing reliability to endure practical use. This new redundancy technique was successfully implemented in the cache memories of a 32-b RISC microprocessor.

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies

This paper describes the circuit technologies and the experimental results for a 1 Mb flash CAM, a content addressable memory LSI based on flash memory technologies. Each memory cell in the flash CAM consists of a pair of flash memory cell transistors. Additionally, four new circuit technologies have been developed: a small-size search sense amplifier; a highly parallel search management circuit; a high-speed priority encoder; and word line/bit line redundancy circuits for higher production yields. A cell size of 10.34 /spl mu/m/sup 2/ and a die size of 42.9 mm/sup 2/ have been achieved with 0.8 /spl mu/m design rules. Read access time and search access time are 115 ns and 135 ns, respectively, with a 5 V supply voltage. Power dissipation in 3.3 MHz operations is 210 mW in read and 140 mW in search access.

Novel electron-beam image-based failure localization techniques

This paper describes three newly developed LSI failure point localization techniques based on voltage contrast imaging with an electron beam tester, two of them are for logic LSI's and one is for memory LSI's. These techniques have already been applied to more than 280 logic and 25 memory LSI's which were found faulty not only in the field but during the LSI development and production stage. Almost all failure causes were successfully identified, allowing the quick corrective action to LSI design or the wafer processing.

An objective lens system for e-beam cell projection lithography

Abstract An objective lens system has been developed for electron beam cell projection lithography for quarter micron LSI. This system features are a 5 μm square maximum shot size, small deflection aberrations in a 5 mm field and high speed three stage deflectors. The experimental aberration coefficients agree well with simulated ones. As a result, cell patterns and 0.15 μm line and space patterns are delineated within a 5 mm field. This lens is applicable to memory and logic LSI fabrication.

Three‐dimensional memory LSI with optical interconnections

AbstractAs devices are miniaturized and device operation speed increases by the progress of fine fabrication technology, the problems associated with interconnections such as interconnect delay and crosstalk are becoming important. Therefore, an optical connection as a new interconnect technique to solve these interconnection related problems is becoming noticed. On the other hand, three‐dimensional LSIs are again becoming noticed as an LSI to overcome the limitations of high integration and to incorporate new functions such as parallel processing function. Consequently, this paper examines the possibility of LSI with new function surpassing the present LSIs by combining the optical interconnection and three‐dimensional LSIs by combining the optical interconnection and three‐dimensional LSI. As an example of this kind of LSI, a three‐dimensional optically coupled common memory is described and the performance improvements are specifically shown by combining the optical interconnection and three‐dimensional LSI.

A CMOS four-channel*1K time memory LSI with 1-ns/b resolution

A four-channel 1024-b time-to-digital converter chip, which records input signals to memory cells at 1-ns intervals, has been developed. To achieve 1-ns precision, the chip incorporates a feedback stabilized delay element. The chip was fabricated on a 5.0-mm*5.6-mm die using 0.8- mu m CMOS technology. It dissipates only 7 mW/channel under typical operating conditions. >

Mubeam system for study of single event upset of semiconductor devices

A high energy heavy ion mubeam system has just been installed on a beam line of the 3 MV tandem electrostatic accelerator mainly for analysis of single event upset (SEU) of LSI memories in spacecraft. This system was designed for precise beam positioning at a desired muscopic area of the mucircuit, to experimentally evaluate of actual SEU sensitive area, and also to allow single ion hits for observing a transient charge pulse from an SEU. For these purposes, a fair amount of target beam current is required for beam positioning at the desired area. The system is equipped with two lens systems: one to control the target beam current in a wide range down to an extremely low current without any change of the beam optics, and the other to focus heavy ion beams within a spot size of 1 μm. The final goal is to hit a muscopic target area with a single 15 MeV nickel ion.

Structure of the test program for vlsi memory devices and its application

AbstractVLSI memories have been diversifying along with high density and high speed. With diversification, the evaluation test program also must handle each VLSI memory, and the efficiency of its generation is an important issue.In this paper, to evaluate diversifying VLSI memories, a program structure is described which can create evaluation test programs quickly for semiconductor test equipment, especially memory testers. The test program presented herein has a module structure consisting of utility groups for evaluation, a main program, and subroutine programs which describe the specific test conditions for each VLSI memory. Also, it can handle the evaluation of various VLSI memories with minimum programming.As a result of using this program structure for the evaluation test programs for 16 kinds of VLSI memories, it has been confirmed that the program development time can be reduced to one‐fifth that of the conventional method and the evaluation time can also be reduced by one hour.

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

A 288-kb (8 K words*36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder is described. The stacked-capacitor structure results in a very compact dynamic CAM cell (66 mu m/sup 2/) which is operationally stable. The novel hierarchical priority encoder reduces the circuit area and power dissipation. In addition, a new priority decision circuit is introduced. The chip size is 10.3 mm*12.0 mm using a 0.8- mu m CMOS process technology. A typical search cycle time of 150 ns and a maximum power dissipation of 1.1 W have been obtained using circuit simulation. In fabricated CAM chips, the authors have verified the performance of a search operation at a 170-ns cycle and have achieved a typical read/write cycle time of 120 ns. >

Development of a solid state sound recorder system

A solid state sound recorder system LSI was developed for use in sound recorder equipment. The LSI used a novel audio compression algorithm and enhanced large capacity memory management to eliminate the need for magnetic tape recording. The LSI used external memory devices to store audio data. Up to 32 Mbit of DRAM (dynamic RAM) can be used, and DRAM, SRAM (static RAM), and ROM can be used individually or in a mixed format for flexibility in system design. The LSI memory control circuitry can automatically detect and bypass a faulty location in memory. The memory management circuits also ensure that there is no delay in recording and replay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Centralized system level redundancy scheme for large‐capacity memory systems

AbstractTo cope with the deterioration of the yield of the memory LSI due to the microstructured design, this paper considers the centralized system‐level redundancy scheme, where, by providing the spare memory chip and the rescue control circuit to the semiconductor memory system, the fault is rescued in a centralized way. In this scheme, the fault bits are memorized in the nonvolatile memory for each word/bit line, and the normal and the spare memories are switched at the I/O terminal of the system by the parallel access.As the method of access to the spare memory, this paper proposes the indirect address input method, where the external address is converted by the control circuit, and the direct address input method, where the external address is directly used. In the former, the external address is converted into the internal address and the ratio of the spare memory to the normal memory decreases with the increase of the system scale, which is favorable to low‐cost applications.The method is applied to the 20‐Mbit file memory using partially good 1 MSRAM, and it is verified that the defect word/bit lines of up to 35 line/chip can be rescued, thereby improving the yield by approximately three times.In the latter method, the addresses to the normal and the spare memories are input simultaneously in parallel, which is favorable for the high‐speed operation. This method is applied to the 4‐Mbit memory module using partially good 4 MDRAM and it is verified that the defect can be rescued while minimizing the deterioration of the access time.

Electron Beam Block Exposure

A new exposure technique called block exposure was examined in order to increase the throughput of direct writing of memory LSI devices using an electron beam. With this technique, an electron beam is projected to a block of aperture patterns in the stencil mask to change the beam shape. Frequently used LSI pattern components are defined as blocks to be reused during the exposure. Patterns that are rarely used are exposed by using a variable-shape beam. With the demagnification ratio of one percent, masks are easy to fabricate and very reliable. The patterns with a 0.13-µm minimum feature size are well projected on a single-layer resist. With block exposure, any shape can be accurately transferred irrespective of the pattern shape or size. The throughput of about ten 8-in wafers per hour is estimated for several pattern layers of a 64-Mbit dynamic random-access memory (DRAM).

Novel content addressable memory

The design and performance of a content addressable memory (CAM) LSI using a newly developed cell circuit is presented. The LSI has all the functions necessary to implement a high-speed data searching system and is fabricated using a 3 mu m CMOS double-metallisation process. A cycle time of 60 ns with the basic associative operation taking 20 ns has been measured.

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode

To realize an efficient redundancy test using the multibit test (MBT) mode, a redundancy flag on a memory LSI tester and an effective redundancy technique which cooperates with the MBT mode have been introduced. This simple redundancy architecture needs only the RFLG (512 bits for the 1 M*1-bit DRAM) as a hardware option on a memory LSI tester. The program development time for the redundancy test has been shortened. Throughput improvement of six to ten times has been achieved in the actual 1-Mb DRAM redundancy test.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

MBE as a production technology for HEMT LSIs

Molecular beam epitaxy (MBE) is widely used to produce high quality epitaxial layers for advanced heterostructure devices. High electron mobility transistors (HEMTs) based on selectively-doped AlGaAs/GaAs heterojunction structures are one of the most successful applications of MBE. This paper reviews MBE techniques developed in our laboratories for HEMT LSI fabrication. To meet material requirements for submicron-gate AlGaAs/GaAs HEMT LSIs, we designed a multiwafer MBE system that enables good uniformity and high throughput. Epitaxial growth is done simultaneously on three 3-inch wafers mounted in a 7.5-inch holder. The variations of layer thickness and carrier concentration over the holder area were less than ±1%. One-touch substrate mounting without indium solder was developed for the t.5-inch holder. In-situ monitoring of growth rates by RHEED instensity oscillation with an automated growth system was introduced to control epitaxial parameters precisely. The density of oval defects due to Ga sources was stably controlled to less than 10 cm -2 and carrier depletion at the substrate-epitaxial layer interface was significantly reduced. These excellent material characteristics make it possible to develop high-performance HEMT logic and memory LSI circuits.

A 20 kbit associative memory LSI for artificial intelligence machines

A 20 kb (512 words*40 b) CMOS associative-memory LSI is described. This LSI performs large-scale parallelism for highly efficient associative operations in artificial intelligence machines. Relational search, large-bit-length data treatment, and quick garbage collection are realized on the single-chip associative-memory LSI. A cell array structure has been designed in order to reduce the chip area. A newly designed simple accelerator circuit allows for high-speed search operations. The LSI is fabricated using 1.2 mu m double-aluminium-layer CMOS process technology. 284000 devices have been integrated on a 5.3*7.9 mm/sup 2/ chip. The measured minimum cycle time and power dissipation at 10 MHz operation are 85 ns and 250 mW, respectively. The associative memory, with its highly efficient associative operation capabilities, promises to be a large step toward the development of high-performance artificial intelligence machines.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high-speed 1-kbit high electron mobility transistor static RAM

A 1-kbit static RAM with enhancement and depletion-mode devices was designed and fabricated using the high electron mobility transistor (HEMT) technology. The RAM circuit was optimized to achieve ultra-high-speed performance. A subnanosecond address access time of 0.6 ns was measured at room temperature for a total power dissipation of 450 mW. The minimum WRITE-ENABLE pulse width required to change the state of memory cell is less than 2 ns on probe testing. The best chip has 3 bits that failed to function, which corresponds to a bit yield of 99.7 percent. According to the simulation, variations of the threshold voltage inside the memory cell greatly reduce its stable functional range. High-speed operation requires more uniform threshold voltage control to achieve fully operational LSI memory circuits.