Memory LSI Research Articles

Test system checks microprocessors and LSI memories : Charles Cohen. Electronics p. 17E (July 1976)

Test system checks microprocessors and LSI memories : Charles Cohen. Electronics p. 17E (July 1976)

Photomask/resist capability—An approach to assessment

The current activity in LSI and high density semiconductor memory development has increased emphasis on the need for the reduction of process-induced defects. An appreciable number of these defects is associated with photofabrication steps due to photomask and/or photoresist variations. In order to minimize defects caused by these steps, it is necessary to determine the type and density of photomask/resist faults that result in any given device defect. The evaluation techniques used should not require highly sophisticated and expensive equipment that would prevent their use in a normal production environment. With these objectives in mind, a test pattern has been designed to evaluate both photomask and photoresist process variables. Test procedures using typical production processes have been developed for this pattern to evaluate such parameters as average alignment accuracy, mask image distortion, etching control, and mask durability. The test pattern and associated evaluation test procedures are described. The more significant aspects are discussed and some illustrative results are presented where appropriate.

A Computer Network for Improved Control

The bases of a practical scheme for integrated control of modern industrial complexes is decomposition and hierarchical organization. Such control scheme requires a new look at the hardware which is needed for its implementation. The proper candidate for such job are not large computers but rather networks of small computers, LSI processor chips and memory chips. A network consisting of such processors and data transmission channels with the processors and the processing loads connected through inteligent interfacing nodes to the data transmission channel is most adequate. This form of realization is the hardware counterpart of the hierachical organization of control and management process.

Orthogonal Latin Square Configuration for LSI Memory Yield and Reliability Enhancement

When errors occur which exceed the correction capability of an error correcting code, the only recourse to restore the original memory function is to physically replace the failed entity. In this paper the authors propose an automatic reconfiguration technique which uses the concept of address skewing to disperse such multiple errors into correctable errors. No additional redundancy other than that required for the error correcting code is needed. The skewing mechanism is derived using the theory of orthogonal Latin squares.

A practical, low-cost, home/school microprocessor system

Despite the recreational and educational potential of stored-program computers, the single factor of cost has kept them out of the economic reach of most people. But with the advent of LSI microprocessor and memory chips, this may all change — particularly if we take a more modest applications approach and place reasonable limitations on hardware capability.

Power Reduction Techniques for LSI Memory

Power reduction techniques are described for both LSI memory components and systems. These techniques have been verified experimentally for both read-only and random access read/write components using power switching circuits external to the chips. A number of ways to apply on-chip power switching are described. The power switching concept is also described for memory cards and systems that can be organized into blocks.

Designing an LSI memory system that outperforms cores—economically : EDN Computer Hardware supplement, 15 January (1971)

Designing an LSI memory system that outperforms cores—economically : EDN Computer Hardware supplement, 15 January (1971)

Design considerations leading to the ILLIAC IV LSI process element memories

The authors present the design considerations for a 256-bit bipolar LSI memory component and the system-packaging technology by which the LSI components were assembled to provide seventy 131 072-bit 200-ns full-cycle main process element memories for the ILLIAC IV computing system. The concepts utilized allow memory modularity from about 1024 bytes to over 3,000,000 bytes while maintaining an approximately linear price per bit over the whole range. The experience on LSI memory component and system testing is discussed. Also included are observations on experiences with component designs and prices during the PEM project.

Modular bipolar LSI memory systems

Modular bipolar LSI memory systems