LPCVD Oxide Research Articles

(Best Paper Award, Invited) Manufacturing of Nanosheets and Multilayer Nanogaps in Silicon

Nanogap technology is the basic concept for many promising devices such as localized SOI, multichannel FETs, and resonant tunneling diodes.It will be shown that intrinsic bulk strain in single crystalline silicon can be used to create homogeneous nanogaps with a few nanometer gap distance. The strain has been created by epitaxial growth of Si1-xGex/Si multi-layer stacks on 200 mm (100) silicon wafers. The stacks were patterned by RIE to reveal the side walls for subsequent lateral etching with gaseous hydrochloric acid. In accordance with former investigations [1] we found that a selectivity up to 1000:1 for Si1-xGex/Si can be achieved for Ge-concentrations >30% and growth temperatures T<650°C. XRD measurements, SEM pictures and wagon wheel test structures prove that for the anisotropic lateral etching behavior intrinsic strain is the dominant factor. Furthermore, the crystal orientation plays a dominant role (Fig. 1). Based on this behavior multilayer nanogaps with spacings <10 nm had been fabricated.In a subsequent process nanogaps down to 5 nm have been successfully filled completely with dielectrics and/or metals by low temperature (T<450°C) plasma oxidation, LPCVD as well as ALD (Fig. 2). The resulting nanosheets can be used for device applications.Vertical diodes and lateral MOS transistors with nanogaps and nanosheets have been fabricated. Diodes with a SiO2 gap filling show perfect Fowler-Nordheim tunneling, which proves the high quality of the gap filling process. The electrical properties of nanogap-MOSFETs and various nanogap-diodes will be presented.[1] Destefanis et al., Semiconductor Sci. Technol. 23, 1 (2008) Fig. 1: Wagon wheel structure showing the etch anisotropy of 8 nm SiGe layer in Si Fig. 2: SEM cross section of a multistack of 6 SiGe layers selectively etched and completely filled with LPCVD oxide

(Invited, Digital Presentation) Improved Reliability of 4H-SiC Metal-Oxide-Semiconductor Devices Utilising Atomic Layer Deposited Layers with Enhanced Interface Quality

A major component of reliability of Silicon Carbide (4H-SiC) power electronics are due to the gate dielectric. Specific aspects such as hysteresis, insulator lifetime, threshold voltage (VTH) instability and high leakage currents, remain an issue of paramount importance which hamper the uptake of 4H-SiC power MOSFETs.1 The oxide understood to have the most importance is coincidently the native oxide, SiO2, due to the suitable band offset to 4H-SiC. However, most of the SiO2/SiC interface problems, such as carbon clusters, H content and O vacancies, are directly related to the thermal oxidation process.2 Here, we show these issues can partially be avoided by using dielectric deposition instead.Atomic layer deposition (ALD) offers specific advantages such as very low deposition temperature, excellent process control and suitability for conformal deposition of gate oxides in trench structures.3 Deposited oxides still require a post-deposition anneal (PDA) in a nitrogen-containing ambient4 such as nitrous oxide (N2O) or nitric oxide (NO) [2] to passivate the defects within the stack and improve the as-deposited layer’s poor electrical quality. We present the excellent reliability performance of ALD-deposited SiO2 layers on SiC through fabrication of metal-oxide-semiconductor capacitors (MOSCAPs) and then using time-dependent dielectric breakdown (TDDB) characterisation. The distribution of interface parameters, as well as the results from TDDB, have been investigated as metrics of improvement following the N2O PDA process. For benchmarking, processes will be compared to thermally grown oxides4 and LPCVD-deposited dielectric layers to demonstrate the superior process quality.An active 10 µm thick epitaxial layer of 4 × 1015 cm-3 n-type doping is used in this study and grown on 100 mm diameter, 4° off-axis (0001) 4H-SiC wafers. Growth was performed using a 30 μm/hr growth and N2 as a dopant in an LPE ACiS M8 chemical vapour deposition (CVD) reactor. After an initial clean, a 1 µm thick field oxide was deposited and a window was opened via photolithography and reactive ion etching (RIE). Then, quarter wafers underwent one of the three oxidation routines: 1. SiO2 plasma deposition at 200 °C using bis(diethylamino)silane (BDEAS) and O2 plasma precursors in an Ultratech Fiji G2 Plasma-Enhanced ALD System. 2. SiO2 deposition at 750 °C using tetraethyl orthosilicate (TEOS) as a precursor in a Thermco LPCVD system. 3. direct thermal growth of SiO2 in a HiTech furnace at 1300 °C for 5 hrs in N2O ambient. Samples that had undergone one of the first two routines then underwent a PDA in N2O, in the HiTech furnace at 1300°C for 2 hrs. All oxidation measurements resulted in oxide thicknesses between 50 and 60 nm, which were verified using step-height AFM measurements and optical interferometry. To create the vertical MOSCAP structure samples had a 500 nm aluminium (Al) backside contact deposited, before a 1 μm Al layer was deposited on the topside of the samples by means of a liftoff process. A cross-sectional diagram of the fabricated final device structure is shown in Fig. 1 (a). Table I shows the key electrical parameters which were extracted using room temperature C-V measurements, combined with I-V and constant field TDDB measurements at 175 °C. Fig. 1 (b) shows the improvement brought about by the N2O anneal, which also results in the average flatband voltage being reduced by more than 10 V to the lowest value of the dataset (1.44 V) and frequency dispersion mostly removed, with all but the ALD as-deposited samples reaching average breakdown oxide fields of about 10 MV/cm. The most promising improvement of the ALD-deposited SiO2 can be seen observing the breakdown distribution of MOSCAPs when stressed at constant high electric field (9 MV/cm), which can be seen in Fig. 2 (a) and (b). Here, these samples reach a TDDB, 63% value of 4786 s, which represents an average increase of 28% when compared to LPCVD samples and 58% when comparing this to a purely thermal process.Further evidence will be presented that high-quality, high-reliability SiO2 layers, formed by ALD and PDA have been formed. Flatband voltage and hysteresis are reduced, compared to thermally grown oxide, and frequency dispersion in accumulation is negligible. The ALD oxide with PDA has higher reliability than LPCVD and thermal oxides in TDDB tests, offering 29% to 345% improvement. The degradation mechanisms of the ALD oxide are different to that the LPCVD and thermal oxides and will be discussed in this talk.[1] P. Moens et al, ISPSD 32, 78-71 (2020).[2] P. Fiorenza et al, Appl. Surf. Sci., 149752 (2021).[3] A. Renz et al, MSSP 122, 105527 (2021).[4] K. Tachiki et al, Appl. Phy. Expr. 13.12, 121002(2020). Figure 1

The effects of etching and deposition on the performance and stress evolution of open through silicon vias

The effects of silicon etching using the Bosch process and LPCVD oxide deposition on the performance of open TSVs are analyzed through simulation. Using an in-house process simulator, a structure is generated which contains scalloped sidewalls as a result of the Bosch etch process. During the LPCVD deposition step, oxide is expected to be thinner at the trench bottom when compared to the top; however, additional localized thinning is observed around each scallop. The scalloped structure is compared to a structure where the etching step is not performed, but rather a flat trench profile is assumed. Both structures are imported into a finite element tool in order to analyze the effects of processing on device performance. The scalloped structure is shown to have an increased resistance and capacitance when compared to the flat TSV. Additionally, the scalloped TSV does not perform as well at high frequencies, where the signal loss is shown to increase. However, the scallops allow the TSV to respond better to an applied stress. This is due to the scallops’ enhanced range of motion and displacement, meaning they can compensate for the stress along the entire sidewall and not only on the TSV top, as in the flat structure.

Depth profiles of refractive index in thermally grown and LPCVD oxide films on silicon

Thin and thick silicon oxide films are grown by thermal oxidation of silicon in dry oxygen or by LPCVD from a mixture of monosilane with oxygen or nitrous oxide. Depth profiles of refractive index are determined in these films by monochromatic ellipsometry, with the measurements interpreted by solving an inverse problem within a multilayer model. The differences between the depth profiles are found to be consistent with well-known mechanisms of film growth under the process conditions applied.

Fabrication of thick silicon dioxide layers for thermal isolation

This paper reports a method of fabricating very thick (10–100 µm) silicon dioxide layers for thermal isolation without the need for very long deposition or oxidation. Deep reactive ion etching (DRIE) is used to create high-aspect-ratio trenches and silicon pillars, which are then oxidized and/or refilled with LPCVD oxide to create oxide layers as thick as the DRIE allows. Stiffeners are used to provide support for the pillars during oxidation. Thermal tests show that such thick silicon dioxide layers can effectively thermally isolate heated structures from neighboring structures within a distance of hundreds of microns. The thermal conductivity of the thick SiO2 is measured to be ∼1.1 W (m K)−1. Such SiO2 diaphragms of thickness 50–60 µm can sustain an extrinsic shear stress up to 3–5 MPa.

Novel High-Q Suspended Inductors on Alumina Ceramic Substrates

ABSTRACTThe growth of the wireless industry over the past ten years has created a need for good quality passive components, and in particular high Q factor inductors. There has been a large amount of work aimed at improving the quality factors of inductors on both silicon and ceramic/insulating substrates. KAIST and other research groups have explored a MEMS technique, releasing the inductor coil to create an air gap between the coil and underpass, on silicon [1]. Typically the inductor coil has been separated by a 50 to 100μm air gap and has required special processing such as a dual exposure photoresist mold [1]. In the present work, suspended inductor coils have been fabricated and characterized on an alumina ceramic substrate [2]. The gap used was only 1μm and this was enough to increase the self-resonance frequency by up to 4GHz after release. The inductor coils were created in 6–10μm thick electroplated gold and the underpass in an aluminum layer. A sacrificial LPCVD oxide layer was used as the released dielectric. In the present study a range of inductance from 1 to 30nH was explored before and after release. The Q factors achieved in this work range from 40 to 70 in the 2 to 10 GHz range, which are some of the best Q factors reported for planar inductors (see Table I). In addition, since the architecture allowed the use of three metal layers, released transformers were also fabricated. They showed promising high frequency performance, which also will be presented. Minimum insertion loss better then –2dB was achieved between 10–12 GHz. The above described process is simple, precise, and manufacturable with the ability to extend the useful range of inductors to higher frequencies (1–10 GHz).

Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage.

Analog characteristics of metal-insulator-metal capacitors using PECVD nitride dielectrics

The frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications. At measurement frequencies of 1.0 MHz, nitride MIM capacitors show capacitance linearity close to that of oxide MIM capacitors, indicating potential for precision analog circuit applications. Due to dispersion effects, however, nitride MIM capacitors show significant degradation in capacitor linearity as the frequency is reduced, which leads to accuracy limitations for precision analog circuits. Oxide MIM capacitors are essentially independent of frequency.

Simplified 0.35-μm flash EEPROM process using high-temperature oxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheral transistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O/sub 2/ anneal at 850/spl deg/C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs.

High-field stressing of LPCVD gate oxides

We have investigated gate oxide degradation as a function of high-field constant current stress for two types of oxides, viz. standard dry and LPCVD oxides. Charge injection was done from both electrodes, the gate and the substrate. Our results indicate that compared to dry oxides, LPCVD oxides show reduced charge trapping and interface state generation for inversion stress. The degradation in LPCVD oxides with constant current stress has been explained by the hydrogen model.

Wet Etching of Doped and Nondoped Silicon Oxide Films Using Buffered Hydrogen Fluoride Solution

Wet etching of various silicon oxide films using BHF solution was studied as a means of post‐RIE wet cleaning to form small contact holes with the designed shape. Measurements show a dependence of etching rate on concentration for thermal and CVD oxide films. Thermal and ECR‐CVD oxide films showed lower etching rates than doped/nondoped APCVD, LPCVD, and PCVD oxide films showed. The etching rate dependence on concentration was linear for the lower etching rate films but nonlinear for the higher etching rate films. This suggests that, for etching of the higher etching rate films, the dominant etching species is , while plays only a small role.

Electrical and physico-chemical characterizations of the [formula omitted] interface

(6H) SiC MOS structures have been investigated by means of electrical and physicochemical characterizations. Al-doped p-type MOS capacitors still suffer from a large oxide charge. Although slightly better than thermal oxides, LPCVD oxides still exhibit similar properties, therefore indicating that the disorder is mainly interfacial. AFM studies do not show significant differences between n- and p-type layers. Characteristics of MOSFET's built on p-type epilayers are also presented.

Process technology for the modular integration of CMOS and polysilicon microstructures

Modular fabrication of polysilicon surface-micromachined structures after completion of a conventional CMOS electronic process is described. Key process steps include tungsten metallization with contact diffusion barriers, LPCVD oxide and nitride passivation of the CMOS, rapid thermal processing for stress-relief annealing of the structural polysilicon film, implementation of a sacrificial spin-on-glass planarization, and the final microstructure release in hydrofluoric acid. Modularity of the process enables independent modification of either the CMOS or the microstructure process sequences. This technology is used in the fabrication of various types of sensors and actuators.

Source/Drain Dislocations and Electrical Leakage in Titanium‐Salicided CMOS Integrated Circuits

This investigation explored the dependencies of source/drain (S/D) dislocation density, test circuit quiescent current, and junction leakage on processing variables in a titanium‐salicided submicron CMOS process using Taguchi methodology. The primary factor affecting both gate and field edge dislocation densities was the type of polysilicon‐to‐metal dielectric (PMD) film. PECVD oxide PMD leads to lower defect densities than LPCVD oxides. Primary factor affecting quiescent current include PMD film type and S/D implant conditions. The observation of both lower dislocation density and lower leakage for similar PMD film type is taken as strong evidence linking dislocations with device electrical performance.

Hot-carrier degradation of submicrometer p-MOSFETs with thermal/LPCVD composite oxide

It is shown that while gate oxides containing thermal/LPCVD composite oxide have lower defect densities than gates using only thermal oxides, they are more susceptible to hot-carrier degradation. The hot-carrier-induced degradation of composite oxides is worse in p-channel MOSFETs than in n-channel MOSFETs. This sensitivity of p-channel MOSFETs is caused by higher electron trapping levels in LPCVD oxides. For 150-AA gate technology, the hot-carrier-degradation resistance of thermal/LPCVD composite gate oxides with a 70-AA or thicker thermal oxide layer approaches that of high-quality pure thermal oxide. >

Reliability of Submicron Mosfet's with Deposited Gate Oxides under F-N Injection and Hot-Carrier Stress

In this paper, submicron nMOSFET's with thin LPCVD gate oxides deposited using chemical reaction of dichlorosilane and nitrous oxide at 800 °C were evaluated. Fowler-Nordheim injection was performed to compare the resistance to electron trapping and interface-state generation of these LPCVD oxides to that of the thermally grown oxides at 850 °C. It was found that with an 850 °C 20-minute post-deposition nitrogen anneal, the LPCVD oxides exhibit comparable immunity to electron trapping as the thermal oxides. Transistor characteristics such as Δg m /g m , ΔI D /I D revealed to be similar for both oxides, but there was an order of magnitude higher ΔV t detected for the LPCVD oxide films (with/without anneal) than the thermal oxides. The mechanism responsible for the hot-carrier induced device degradation was also characterized in this study. It was found that the major source of hot-carrier damage was electron trapping for the thermal oxides and the N 2 - annealed LPCVD oxides; while for the as-deposited LPCVD oxides, both electron trapping and interface-state generation contributed to device degradation.

Self-aligned bipolar transistor using double thermal oxidation

A novel process is proposed to self-align the emitter and extrinsic base in a bipolar transistor. The process involves the use of double thermal oxidation and RIE to create a steep oxide emitter sidewall. The method avoids the potential problems of LPCVD oxide and can remove the residual poly on the extrinsic base, both of which lead to base-emitter shorts. It also eliminates the need for growth of adhesion oxide and annealing of LPCVD oxide. The devices thus fabricated exhibit a high current gain of 130 and high punchthrough voltage of 20V.

Hot-electron trapping in thin LPCVD SiO2dielectrics

The electron-trapping and surface-state generation characteristics of thin LPCVD SiO 2 dielectrics have been studied using avalanche hot-electron injection. Layered structures of thermal and LPCVD oxide have been examined as a function of anneal time and temperature. After a 1000°C anneal, bulk trapping in the LPCVD oxide was reduced to levels comparable to those in a high-quality dry thermal oxide. Sensitivity to remaining traps was reduced by the presence of a thermal oxide layer on the semiconductor surface. After a post-deposition anneal (PDA), these layered surfaces demonstrated hot-electron performance equal to that of thermal oxide within measurable limits. Also, layered structures generally demonstrated better resistance to surface-state generation than thermal oxides alone. Since less chlorine is incorporated into the layered structures during fabrication, this result is consistent with a recent model identifying broken chlorine bonds as the origin of surface states.

Electrical properties of silicon dioxide films fabricated at 700°C. II: Low pressure hydride deposition

We have investigated the effects of different annealing treatments on silicon dioxide films produced from the reaction of dichlorosilane and nitrous oxide at 700° C. The electrical quality of these LPCVD films was evaluated by measuring oxide charge and interface trap densities on metal oxide semiconductor (MOS) capacitors. These densities were measured before and after avalanche injection of electron currents into the oxide films. The results of these studies were as follows. (1) The LPCVD oxide films required a post deposition anneal at 1000° C to produce as-grown charge densities similar to those of a standarddry thermal oxide grown and annealed at 1000° C. (2) Post-injection charge densities of LPCVD films given a post deposition anneal at 1000°C were an order of magnitude greater than those of the standard dry thermal oxide. (3) Different annealing treatments produced a series of dominant electron trapping centers in the oxide bulk17 with capture cross sections ranging from 10−14 cm2 to 10−17 cm2. (4) The electron traps in the LPCVD oxides films were similar to those previously observed in standardwet thermal oxides grown and annealed above 1000° C.

Electrical properties of silicon dioxide films fabricated at 700°C. I: Pyroltsis of tetraethoxysilane

We have studied the effects of different deposition and annealing ambients on silicon dioxide films produced via the pyrolytic decomposition of tetraethoxysilane at 700° C. The oxide and interface charge characteristics of capacitors incorporating these oxides were measured. The results of these studies were as follows. (1) Films deposited in nitrogen exhibited very poor electrical properties. This was due to the poor quality of both the LPCVD oxide bulk (manifest as a hysteretic instability exceeding one Volt in 20 nm films) and the LPCVD oxide-silicon interface (interface trap charge and fixed charge exceeding 1012 cm−2). These characteristics were not improved by post-deposition annealing in nitrogen at 700° C. (2) As much as an order-of-magnitude reduction in interface traps and/or bias-induced drifts was obtained by exposure of the silicon substrate to 700°C oxygen ambients before, during, or after pyrolysis. The maximum improvement also required both post-deposition and post-metallization annealing treatments in nitrogen.