Source/Drain Dislocations and Electrical Leakage in Titanium‐Salicided CMOS Integrated Circuits

Abstract

This investigation explored the dependencies of source/drain (S/D) dislocation density, test circuit quiescent current, and junction leakage on processing variables in a titanium‐salicided submicron CMOS process using Taguchi methodology. The primary factor affecting both gate and field edge dislocation densities was the type of polysilicon‐to‐metal dielectric (PMD) film. PECVD oxide PMD leads to lower defect densities than LPCVD oxides. Primary factor affecting quiescent current include PMD film type and S/D implant conditions. The observation of both lower dislocation density and lower leakage for similar PMD film type is taken as strong evidence linking dislocations with device electrical performance.