Low-temperature Polycrystalline Silicon Research Articles

LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension

A low leakage poly-Si thin film transistor (TFT) is proposed featuring hydrogenated amorphous silicon (a-Si:H) buffer layer and source/drain extension (SDE) by using technology computer aided design (TCAD) simulation. This architecture reduces off-current effectively by suppressing two leakage current generation mechanisms with little on-current loss. The amorphous silicon buffer layer having large bandgap energy (Eg) suppresses both thermal generation and minimum leakage current, which leads to higher on/off current ratio. In addition, the formation of lightly doped region near the drain alleviates the field-enhanced generation in the off-state by reducing electric field. TCAD simulation results show that the proposed TFT shows more than three orders of magnitude lower off-current than low-temperature polycrystalline silicon (LTPS) TFTs, while maintaining on-current.

Analysis of the transient body effect model for an LTPS TFT on a plastic substrate

This work investigates the transient current in the subthreshold region of a low-temperature polycrystalline silicon thin-film transistor (LTPS TFT) on a polyimide (PI) substrate. The measurement of this current shows an instability that is not seen in the device on a glass substrate; the instability appears as a current variation under constant voltage and overshoot or undershoot under external stress voltage transitions. To explain this effect for a TFT on a PI substrate, a transient body effect (TBE) is suggested due to a threshold voltage shift caused by the charge distribution inside the substrate. A SPICE model is proposed based on this concept, and it shows excellent agreement with device measurements. The model offers a simulation guideline for LTPS TFTs on PI substrates.

Multi-Level Memory Comprising Low-Temperature Poly-Silicon and Oxide TFTs

In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.

A Low-Power Memory-in-Pixel Circuit for Liquid Crystal Displays Comprising Low-Temperature Poly-Silicon and Oxide Thin-Film Transistors

In this paper, a new pixel structure using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistors (TFTs) for low-power liquid crystal displays (LCDs) is proposed. The extremely low off-state current of oxide semiconductor TFTs enables the proposed circuit to operate at a very low frame frequency of 1/60 Hz, so that the power consumption can be significantly reduced. In addition, the low-temperature polycrystalline silicon TFTs with high reliability directly drive pixels, which can achieve stable and flicker-free LCDs. The proposed circuit is fabricated using the LTPO TFT backplane and successfully verified by simulation and measurement results. The measurement results prove that the proposed circuit operates well without further programming for 60 s, and the power consumption in the panel (except backlight power) can be reduced to 0.02% of that of conventional LCD.

Suppression of Edge Effect Induced by Positive Gate Bias Stress in Low-Temperature Polycrystalline Silicon TFTs With Channel Width Extension Over Source/Drain Regions

This study demonstrated that the edge effect induced by positive gate bias stress (PBS) was effectively eliminated by applying channel width extensions over source/drain regions in low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). After PBS, a stress-induced hump current in subthreshold region is observed and is caused by the charge trapping into parasitic transistors along the channel width edges. This phenomenon is attributed to carrier injection occurring along the width edges since a high electric field is located at that region, where lots of defects are generated due to the definition of the active area during the etching process. In this study, we show that the degradation in electrical characteristics during the gate bias operation resulted from the edge effect can be eliminated when the TFT devices utilize the channel width extension in the active layer. Electrical measurements, numeral calculations, and a TCAD electrical simulation confirm that this geometry, which includes a channel extension along the width direction, can dramatically reduce the carrier injection at the edges even though high electric field is mainly located at the width edges during gate bias operation.

Various Reliability Investigations of Low Temperature Polycrystalline Silicon Tunnel Field-Effect Thin-Film Transistor

Various reliability issues of low temperature polycrystalline silicon (LTPS) tunnel field-effect transistor (TFET) are comprehensively studied for the first time and compared with conventional LTPS thin-film transistor (TFT). For the positive and negative gate bias stress (P/NGBS) instability, the NGBS causes more serious electrical degradation for both LTPS-TFETs and TFTs because of the higher trap state generation after the NGBS. However, the local P/NGBS near the source-side and drain-side regions show completely different impacts on the LTPS-TFETs and TFTs. The results reveal that the source-side local P/NGBS dominates the entire P/NGBS effects of LTPS-TFETs, and the drain-side local P/NGBS effects have less impacts on the electrical behavior of LTPS-TFETs compared with the entire P/NGBS effects. For the LTPS-TFTs, the local P/NGBS effects show much less electrical degradation than the entire P/NGBS. The difference of local P/NGBS effects between LTPS-TFETs and TFTs is attributed to the different carrier transport mechanisms. In addition to the P/NGBS effects, the hot carrier stress (HCS) with different drain stress voltages is also studied in this work. The drain stress voltage would introduce the horizontal electric field near the junction and reduce the impact of the vertical electric field in the channel region. For the HCS of LTPS-TFETs, the increase of drain stress voltage only leads to the reduction of vertical electric field stress effect but no horizontal electric field stress effect, which is different from the results of LTPS-TFT.

Journal of the Society for Information Display

Jiun-Haw Lee Editor in Chief The Journal of the Society for Information Display's (JSID's) September and October 2020 issues each feature six papers that report on new research in key areas. Topics include OLED, LCD, thin-film transistors (TFTs), electrophoretic displays, human factors, display measurements, and optics. Furthermore, as a friendly reminder, the 26 “Distinguished Papers, Best of Display Week 2020” published in JSID's April, May, and June 2020 issues will remain open access until the end of the year. A single-cell-gap transflective blue-phase liquid crystal display based on fringe in-plane switching electrodes|Xiang-Yu Zhou et al.|doi:10.1002/jsid.872 In this work, the authors propose a new LCD mode for a transflective blue-phase (TRBP) device, which they refer to as fringe in-plane switching (FIS). This mode combines the advantages of in-plane switching (IPS) and fringe-field switching (FFS). Compared to FFS, FIS has a similar driving voltage but with much higher transmittance. However, FIS has a much lower driving voltage than the IPS mode. By providing fringe and in-plane electric fields simultaneously, the authors obtained a deep-penetrating electric field that greatly improved LCD's transmittance while also lowering the driving voltage. Note that two TFTs were required in a single pixel of FISTRBP-LCD for providing the driving voltage with opposite polarities. Investigation on Ag-containing compound generated in manufacturin go flow-temperature polycrystalline Si active matrix organic light-emitting diode |Yu Jin et al.| doi:10.1002/jsid.895 In this highly practical paper, the authors analyze low-temperature polycrystalline silicon (LTPS) active matrix (AM) OLED's failure caused by silver (Ag) contamination, and explore possible solutions. In observing Ag-contamination in LTPS's real products, they noticed that it resulted in short circuits in certain places. The Ag-compounds originate from the electrochemical formation and are related to migration assisted by an electric field. The authors proposed several methods to alleviate this effect, including a planarization dam that can be used to increase the migration path and weaken the electric field. The paper may stimulate interesting ideas for improving production yield without increasing the complexity during display manufacture. Information About the Journal JSID is published monthly by Wiley. Subscription fees apply, but SID members and student members have free online access via sid.org/Publications.aspx. Many universities also have an institutional subscription. JSID is indexed in the Web of Science. Submit your original manuscript online via mc.manuscriptcentral.com/sid. Author guidelines can be found on the Journal's homepage: tinyurl.com/jsidhome. Editorial board: tinyurl.com/jsideb. Please direct any questions about JSID to its editor in chief at editor@sid.org. EarlyView: accepted papers about to be published can be accessed online via tinyurl.com/jsidev. Invitation to Submit Review Papers The Journal is soliciting review papers on any display-related topic. If you have a great idea for a review paper, please contact the editor at editor@sid.org. Page charges for invited review papers will be waived.

Edge-Directed LTPS Via Flash Lamp Annealing Using a Cr Adhesion Layer for Improved Wettability

Flash lamp annealing (FLA) has been explored as an alternative to excimer laser annealed low-temperature polycrystalline silicon (LTPS) for display applications and has shown potential to streamline and decrease the cost of fabrication while maintaining electrical performance [1], [2]. In this method, amorphous silicon is exposed to a single pulse of light emitted from a xenon flash lamp, causing melting and recrystallization in an area of cm2 rather than nm2 in less than a millisecond. FLA has shown value in crystallizing silicon and activating dopants in both PFET and NFET thin-film transistors (TFTs) [3]. However, FLA suffers from inconsistent material uniformity, a consequence of large areas of silicon melting simultaneously. This can cause the molten silicon to de-wet from the oxide or nitride underlayer, leading to the formation of numerous randomized voids. Though previous studies have shown encouraging results when using this void-associated LTPS morphology, improved structure control is necessary to reduce the variance of FLA-LTPS device operation.Edge-directed LTPS has a distinctly different macroscopic morphology than the void associated material, with potential advantages in uniformity and electrical performance. Differences between these morphologies have been previously discussed [4], however in that work the realization of the edge-directed material was hardly intentional and the formation mechanism was not clearly determined. A repeatable and controllable method of producing edge-directed LTPS would effectively solve a key obstacle towards industrial integration of FLA, that of randomly-dispersed irregularities and material nonuniformity.In this work, a replicable morphology of FLA-LTPS is produced and analyzed by using a thin chromium underlayer to promote adhesion without rendering the silicon entirely conductive. With thickness reduced to < 10 nm, Cr does not absorb damaging amounts of energy from the FLA pulse, as opposed to other metal and ceramic layers, which could improve wettability. Chrome has been applied as a silicon underlayer in thin-film photovoltaic applications [5]. The result of this Cr adhesion layer beneath an a-Si mesa during FLA is a characteristic ridge-like pattern of grain formation, as shown in Figure 1A. Large, elongated domains oriented perpendicular to the edges of the silicon mesas are clearly visible. An abrupt ridge is seen equidistant between the long edges of this mesa, with further diagonal ridges present at a 45° angle from the corners. This structure suggests a propagation of crystallization that begins at the edge of the mesas and travels inwards, terminating when it reaches another advancing crystallization front. This structure is only realized when the Cr layer is a continuous film rather than discrete microparticles, suggesting that the effect is due to adhesion rather than metal-induced crystallization. Without this adhesion layer, the randomly-irregular structure seen in Figure 1B is produced. Figure 1C demonstrates atomic force microscopy on this ridge morphology. In this structure, a maximum height differential of around 55 nm between the tops of ridges and the lowest point on the mesa is demonstrated (ignoring scanning artifacts). This is significant, as the original thickness of amorphous silicon as deposited was only 60 nm, suggesting large-scale mass transfer during crystallization. However, dewetting behavior is minimized. The elongated structure, lack of voids, and edge-inward pattern of this morphology is hypothetically consistent with explosive crystallization [6], versus a quasi-equilibrium melt-phase which results in randomly-irregular material.Similar morphology has been demonstrated using excimer laser and continuous-wave laser annealing, in which only a small area of silicon is in liquid phase at any given moment [7], [8]. However, its formation in FLA, in which large areas are melted simultaneously, is an important step towards the commercial viability of flash lamp annealing. This polycrystalline material is being explored as a viable channel material for PFET TFTs. The apparent presence of micrometer-scale grains is expected to improve channel mobility [9], while providing a uniform and predictable structure, thus minimizing variance in device operation. Material properties and electrical characteristics will be presented. Figure 1

Effect of Glass Substrate on the Film Properties of Poly Silicon by Excimer Laser Annealing

This work studies the effect of glass substrate thermal properties on the crystallization behavior and surface topography of polycrystalline silicon (poly-Si) films formed by a XeCl excimer laser annealing of amorphous silicon. Films of 60 nm hydrogenated amorphous silicon (a-Si:H) film were deposited on different glass substrates of varying thermal properties. A 500 nm SiO2 buffer layer was in between the glass and the silicon film. The silicon was crystallized by a XeCl excimer laser. The atomic force microscopy (AFM) and in-plane X-ray diffraction (IPXRD) were used to evaluate the surface topography, the surface roughness, and crystalline in-plane orientation of poly-Si, respectively. Grazing incidence X-ray diffraction (GIXRD) was employed to quantify the residual stress in poly-Si film. The film properties of poly-Si exhibit a small relationship with the glass thermal properties. The higher thermal conductivity of glass retards the poly-Si <111> texture and reduced the residual tensile stress. The higher thermal diffusivity of the glass causes a decline in the poly-Si <111> texture, the surface asymmetry and flatness. A light shield introduced between glass and buffer layer in the low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) structures, further weakens the impact of the glass substrate on excimer laser annealing (ELA) poly-Si properties.

Organic light‐emitting diode display pixel circuit employing double‐gate low‐temperature poly‐Si thin‐film transistor and metal‐oxide thin‐film transistors

AbstractAn organic light‐emitting diode (OLED) display pixel circuit composed of a double‐gate (DG) low‐temperature polycrystalline silicon (LTPS) thin‐film transistor (TFT) and metal‐oxide (MO) TFTs is reported. Two control lines used to initialize the gate‐to‐source bias (VGS) of the driving TFT in the conventional pixel circuit are eliminated by modulating the bottom gate bias (VBS) of the DG‐LTPS TFT. Low leakage current of MO TFT enables us to adopt the simultaneous‐emission scheme for arbitrary compensation time setting and 1‐Hz frame rate driving for low power consumption without flicker. The proposed circuit exhibits better compensation results and smaller area compared with the conventional low‐temperature polycrystalline silicon and oxide (LTPO) pixel circuit. The pixel density of 538 pixels per inch (ppi) has been obtained employing 2‐μm design rule.

An AMOLED Pixel Circuit With a Compensating Scheme for Variations in Subthreshold Slope and Threshold Voltage of Driving TFTs

This article proposes an active-matrix organic light-emitting diode (AMOLED) pixel circuit for mobile displays with high resolution to improve the image quality of the display panel. The proposed pixel circuit, which consists of six low-temperature polycrystalline silicon thin-film transistors (TFTs) and two capacitors, compensates for variations in the threshold voltage (Vth) and subthreshold slope (SS) of driving TFTs at low gray levels. Such compensations are achieved by extending the compensation time in the diode-connection scheme, resulting in a reduction in the OLED current error (OCE) of the proposed pixel circuit. In addition, the proposed pixel circuit connects two capacitors in parallel to the gate node of the driving TFT, thus increasing the total storage capacitance value in a given capacitor area in the emission phase, resulting in a reduction in voltage distortion at the gate node. Moreover, the OCEs caused by the IR drop of ELVDD and the crosstalk due to parasitic capacitances are thoroughly investigated and analyzed. The measurement results of the proposed pixel circuit show that the OCEs at the 64th and 128th gray levels are reduced from ±3.5 and ±6.5 to ±2.0 and ±0.8 LSB, respectively, by extending the compensation time from 6.5 to 195 $\mu \text{s}$ . Therefore, the proposed pixel circuit is highly suitable for mobile AMOLED displays requiring high image quality.

Flash Lamp Annealed LTPS TFTs with ITO Bottom-Gate Structures

Low-Temperature Polycrystalline Silicon (LTPS) thin-film transistors (TFTs) are usually built as a top-gate structure. This is due to the serious challenge presented by locally crystallizing a thin layer of amorphous silicon that has regions of overlap with an absorptive and thermally conductive gate electrode and areas of thermally insulating glass. Early attempts to create LTPS devices quickly switched from the industry standard of bottom-gate to the more attainable top-gate, in which a gate structure is deposited subsequent to crystallization [1]. Despite this difficulty, bottom-gate devices offer potential benefits in breakdown voltage and dielectric-semiconductor interface quality, as well as being a requirement for double-gate devices and enabling higher fill-factor pixel designs in TFT display backplanes. Bottom-gate TFTs have been realized with crystallization via excimer laser annealing (ELA) with a demonstrated improvement over top-gate devices [2]. This is of particular interest for the development of LTPS devices that employ an alternative crystallization technique, such as metal-induced lateral crystallization [3, 4] and continuous-wave laser annealing [5, 6], motivated by potential advantages in large-panel manufacturing.FLA (Flash lamp annealing) has been explored as an alternative to ELA LTPS [7], and has the potential to streamline and decrease the cost of fabrication while providing applicable electrical performance. In this method, amorphous silicon is exposed to a single pulse of light emitted from a xenon flash lamp, causing melting and recrystallization in an area of cm2 rather than nm2 in less than a millisecond. FLA has shown value in crystallizing silicon and activating dopants in both PFET and NFET TFTs [8]. Early attempts to produce bottom-gate FLA-LTPS TFTs were ineffective; the high degree of light absorption and reflectivity in metal or polysilicon gates resulted in severe, localized ablation of the overlying channel silicon. Reducing FLA emission intensity prevented this catastrophic channel loss, but also reduced the crystallization of source/drain region silicon to the point where device performance was dominated by series resistance.In this work, bottom-gate LTPS TFTs are realized using FLA by incorporating indium-tin oxide (ITO) as a transparent conductive gate electrode material. The reduction in absorbance and reflectivity, as well as the enhanced thermal and chemical stability, of ITO allows for the simultaneous, comparable crystallization of both channel silicon above the gate and adjacent source/drain silicon regions above SiO2 and glass substrate. A finalized ITO bottom-gate PFET is shown in Figure 1A and an in-progress image after FLA and ion implantation in 1B. A distinction is visible between silicon over the gate and freestanding silicon, with an even sharper distinction between implanted source-drain silicon over the gate and the true, non-implanted channel. It is clear that the presence of an ITO gate locally enhances silicon crystallization with a slight lateral bleed, but this effect does not dominate to the point of damaging the channel. A subsequent 630 °C furnace treatment provides for both dopant activation and recrystallization of amorphized regions.P-channel TFTs fabricated with ITO bottom gates demonstrated excellent device performance, as shown in Figures 1C and 1D. The ION/IOFF ratio is between 6 and 7 orders of magnitude with notably low off-state leakage. The typical device shown exhibits a threshold voltage VT ~ -5.0 V. The channel mobility was extracted using the maximum transconductance method, indicating a hole µch ~ 190 cm2/Vs. Most transfer characteristics experienced significant degradation at higher drain bias conditions for reasons still under investigation. Nevertheless, these preliminary results provide direction for further investigation, which include the study of a double-gate structure for comparisons in device performance and stability. The additional presence of a top gate will improve electrostatic control of the channel charge, mitigating problems caused by interface trap states with an effect similar to enhanced channel passivation. Further passivation efforts using hydrogen/nitrogen plasma treatments will be incorporated in tandem; these are more effective on bottom and double-gate structures due to easier channel access at the processing back-end. In addition, FLA is being explored as a replacement for the long furnace anneal currently used for dopant activation. Figure 1

Improved Long-Term Stability of Low-Temperature Polysilicon Thin-Film Transistors by Using a Tandem Gate Insulator with an Atomic Layer of Deposited Silicon Dioxide

In this study, we report a substantial improvement in the long-term stability of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) with a tandem gate insulator composed of silicon dioxide (SiO2) deposited by using atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD). Negative-bias temperature instability (NBTI) tests showed that threshold-voltage (ΔVth) shifts were significantly smaller than when only a plasma-enhanced chemical vapor deposition (PECVD) structure was used. We believe that the unique stoichiometric characteristics and the reduction in the interfacial trap density (Dit) produced by the SiO2 gate insulator that had been fabricated using ALD enhanced the long-term stability of the LTPS TFTs. These results suggest a tandem structure gate insulator with high-quality ALD-based SiO2 thin film can provide an important improvement in the characteristics of the p-channel LTPS TFTs required for advanced active matrix organic light-emitting diodes (AMOLEDs) applications.

24‐3: Complementary LTPO Technology, Pixel Circuits and Integrated Gate Drivers for AMOLED Displays Supporting Variable Refresh Rates

A Complementary Low‐temperature Poly‐Crystalline Silicon and Oxide (LTPO) technology based on p‐type Low‐temperature Poly‐Crystalline Silicon (LTPS) and n‐type oxide Thin‐Film Transistors (TFTs) was developed and demonstrated. New pixel circuits and Gate‐on‐Array (GOA) circuits were designed and fabricated using this technology. By combining the superior driving capability of LTPS and ultra‐low leakage of oxide semiconductor, all the pixel circuits and GOA circuits can operate between 1 Hz and 120 Hz, which enables both high refresh rate and low standby power display applications.

Influence of flexible substrate in low temperature polycrystalline silicon thin-film transistors: temperature dependent characteristics and low frequency noise analysis

The carrier transport of p-type low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) on flexible substrate has been intensively studied and compared to that on glass substrate in order to improve device performance. To investigate the origin of carrier transport on different substrates, temperature dependent characterizations are carried out for electrical device parameters such as threshold voltage (VTH), subthreshold swing (SS), on-current (Ion) and effective carrier mobility (μeff). The poly-Si grain size Lgrain and the barrier height EB between grain boundaries are well known to be the main parameters to determine transport in polycrystalline silicon and can be extracted based on the polycrystalline mobility model. However, our systemic studies show that it is not grain size but EB that has more influence on the degradation of LTPS TFT on flexible substrates. The EB of flexible substrate is roughly 18 times higher than glass substrate whereas grain size is similar for both devices on different substrates. Compared to the LTPS TFT on glass substrate, higher EB degrades approximately 24 % of Ion, 30 % of SS and 21 % of μeff on the flexible substrate at room temperature. From low frequency noise (LFN) analysis, it is observed that the total trap density (Nt) for flexible substrate is up to four times higher than that of glass substrate, which also supports the high value of EB in the device fabricated on the flexible substrate.

TCAD Simulation of the Electrical Characteristics of Polycrystalline Silicon Thin Film Transistor

&#x0D; Low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied because of their high performance in Active Matrix Liquid Crystal Displays (AMLCD's) and Active Matrix Organic Light-Emitting Diode (AMOLED) applications. The purpose of this work is to simulate the impact of varying the electrical and physical parameters (the interface states, active layer's thickness and BBT model) in the transfer characteristics of poly-Si TFT to extract the electrical parameters like the threshold voltage, the mobility and to evaluate the device performance. The device was simulated using ATLAS software from Silvaco, the results show that the electrical and physical parameters of poly-Si TFT affect significantly its transfer characteristics, choosing suitable parameters improve high-performance transistor. Such results make the designed structure a promising element for large-scale electronics applications.&#x0D; &#x0D; &#x0D;

Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors

The extent of the poly-silicon crystalline protrusion, a result of differences in excimer laser annealing (ELA), affects the performance and reliability of thin-film transistors (TFTs). This study investigates the degradation mechanism of the low-temperature polycrystalline silicon (LTPS) TFT devices with differences in crystalline protrusion under self-heating stress (SHS). Higher ELA energy will induce higher protrusion height in the interface between the poly-silicon and gate insulator (GI). This surface morphology leads to serious charge trapping into the GI layers; in contrast, the smallest degradation after SHS can be seen in the devices with the lowest protrusion height. This indicates that the degradation is caused by the surface morphology between the poly-Si and GI interface. In addition, the COMSOL simulation results confirm that the large electric field in the GI layer appears in the rough surface morphology devices; therefore, choosing the appropriate ELA energy of the poly-Si is beneficial for the applications of the driving TFT in organic light-emitting diode (OLED) display in the manufacturing industry.

LG PURSUES TWO‐TIER SMARTPHONE STRATEGY

ALTHOUGH LG ELECTRONICS HAS BEEN DRUMMING UP INTEREST FOR ITS NEW premium smartphone, the LG Velvet, the company continues to pursue the lower end of the market as it seeks to turn around its mobile fortunes. LG launched a new budget LTE model, the Q61, into the Korean market in May with a price tag of 369,600 KRW (approximately $306). It is essentially a rebranded version of the LG K61, which was introduced in February 2020 and has hit the market already in Mexico, Brazil, and Canada. The Android-based Q61, which meets US military-grade durability standards, has a 6.5-inch 19.5:9 1,080-pixel LCD, a 2.3-gigahertz MediaTek chipset, 48 gigabytes of storage, and a 4,000-milliampere-hour battery. It also has a 16-megapixel (MP) front camera and a rear quad-camera array with a 48-MP main camera, wide-angle lens, depth sensor, and macro lens. Sales for LG's mobile communications unit dropped 34 percent for the first quarter of 2020 on a year-over-year basis, from 1,510 billion KRW ($1.25 billion) in Q1 2019 to 998.6 billion KRW ($828 million) in Q1 2020. Its operating loss also widened during the same period, from 203.5 billion KRW ($169 million) in Q1 2019 to 237.8 billion KRW ($197 million) in Q1 2020. LG had a 2 percent share of the global smartphone market in Q1 2020 with 5 million units shipped, according to Counterpoint Research, and a 10 percent share of the US market. Although LG already had reduced expenses and labor costs for the mobile unit, the company took a big hit in Q1 because of COVID-19's impact on Chinese equipment suppliers as well as decreased demand from retail store shutdowns, leading to the increased loss, according to its earnings release. OLED displays are steadily gaining share in the smartphone market, particularly at the high end, but LCD still comprises the majority, particularly among 4G models, notes Ross Young, founder and CEO of Display Supply Chain Consultants. While LG Display is winding down LCD panel production for TV sets in Korea this year and scaling back LCD production for other markets such as notebooks and monitors, he expects its low-temperature polycrystalline silicon (LTPS) LCD fabrication plant (fab) in Gumi, South Korea, will continue making LCD mobile displays through 2025. A New Top-shelf Phone LG's premium Velvet series. Image: Courtesy of LG That said, Young thinks LG's more interesting phone launch is the Velvet, which has an OLED display and a price tag of 899,800 KRW ($746). The Velvet has a mid-range Qualcomm processor, a unique waterdrop rear camera design, and a thin, curved body that can be inserted into a special dual-screen case to provide much of the functionality of a foldable phone. Another intriguing aspect of the Velvet, says Young, is that its OLED display is being supplied by China's BOE, not LGE's corporate cousin LG Display. That's because LG Display has dedicated its burgeoning mobile OLED display production in 2020 to Huawei and Apple, which are the second and third highest original equipment manufacturers (OEMs) in terms of total global shipments, behind Samsung Electronics. He adds that 2020 should be a “good growth year” for LG Display's mobile OLED business, with total panel shipments forecast to grow from 12 million units in 2019 to 32 million units in 2020. Young expects Apple to buy 20 to 25 million of those panels for the new 5G phones it's launching this fall. As a result, he predicts LG Display's share of the OLED mobile display market to make a commensurate leap, growing from around 4 percent in Q1 2020 to perhaps 8 percent by Q4 2020. —Glen Dickson

Resilience of Fluorinated Indium-Gallium-Zinc Oxide Thin-Film Transistor Against Hydrogen-Induced Degradation

Thin-film transistors (TFTs) based on amorphous indium-gallium-zinc oxide (IGZO) with or without plasma fluorination treatment were fabricated and the sensitivity of their characteristics to hydrogen exposure was compared. Consistent with the lower hydrogen content revealed using secondary ion-mass spectrometry, TFTs built with fluorinated IGZO were shown to exhibit improved intrinsic resilience against hydrogen-induced degradation. Further enhanced by the incorporation of aluminum oxide as a hydrogen diffusion-barrier, such resilience is beneficial to the integration of fluorinated IGZO TFTs with hydrogen-containing devices, such as photodiodes based on amorphous hydrogenated silicon and TFTs based on low-temperature polycrystalline silicon.

Total-Dose Effect of X-ray Irradiation on Low-Temperature Polycrystalline Silicon Thin-Film Transistors

In this paper, the total-dose effect of X-ray irradiation on low-temperature polycrystalline-silicon (LTPS) thin film transistors (TFTs) is studied. Experiments under different conditions, including fixed intensity, fixed time, fixed total dose, short shot with different frequencies and high/low intensity for short/long time were performed and analyzed. With an increase of the irradiation dose, the threshold voltage ( ${V}_{ {th}}$ ) shifts negatively, the subthreshold swing ( $S.S$ .) degrades and the field effect mobility decreases owing to positive trapped charges and interface traps. All magnitude of negative shifts of ( ${V} _{ {th}}$ ), ( $ {S.S.}$ ) and field effect mobility for LTPS TFTs are well correlated to the total accumulated dose. The results are consistent with ( ${V} _{ {th}}$ ) shift due to trapped holes and the interface traps for mobility.