Lower Technology Nodes Research Articles

Impact of deep cryogenic temperatures on gate stack dual material DG MOSFET performance: Analog and RF analysis

By understanding the potential benefits of Gate Stack Dual Material double gate MOSFET (DG MOSFET), this research aims to contribute to the investigation of its electrical characteristics with improved performance and dependability. A detailed investigation is conducted into the temperature dependent electrical properties at different temperatures. A detailed analysis is conducted on the enhanced gate controllability in lower technology nodes and the protection against short channel effects. Together with the DC performances, this research also analyzes the suggested device's analog performance. The device's performance matrix was presented for temperatures ranging from 70 K to 800 K. The results showsthe improvement the drain current, transconductance, and transconductance generation factor(TGF) with decrease in temperature.

Green chemical mechanical polishing of copper with 2,5-dihydroxy-1,4-dithianeas as the inhibitor: Experimental and theoretical studies

It is a great challenge to develop green chemical mechanical polishing (CMP) technique owing to the limited inhibitory performance of green inhibitors. In this study, 2,5-dihydroxy-1,4-dithiane (DHD) was found and utilized as a superior inhibitor in CMP slurry, which realized nanometer-scale smoothness for copper surface. The strong inhibition effect of DHD, in both static and dynamic situations, was demonstrated by microscopic observations and electrochemical characterizations. The effectiveness of DHD was achieved mainly through its chemisorption onto copper surface, determined by Langmuir adsorption isotherm. X-ray photoelectron spectroscopy and density-functional-theory calculations proved that the chemisorption occurred between the S atom of DHD and Cu. Overall, DHD as an efficient and eco-friendly inhibitor with low-cost exhibits immense potential for applications in chip fabrication, particularly at a low technology node.

Novel hybrid-CMOS inverter utilizing phase transition material for enhancing digital logic performance at lower operating voltages

This research paper introduces a novel design for a hybrid-CMOS inverter using vanadium dioxide (VO2), a phase transition material. The proposed inverter exhibits a remarkably steep transition for falling logic at the output(1–0). By leveraging the insulating to metallic current density (IC-IMT) of VO2, the depth and gain of this transition can be finely tuned. Notably, a higher IC-IMT value yields a greater gain in the transition slope. In comparison to a traditional CMOS inverter, the designed inverter demonstrates several advantages. It achieves higher values of lower noise margin (NML) and significantly reduces static power dissipation by 97.7%. These promising outcomes present an exciting opportunity for designing inverters at lower drain voltages, especially in devices operating at lower technology nodes. Furthermore, the hybrid-CMOS inverter is designed to excel in the sub-threshold region of operation, resulting in elevated values of lower noise margin and reduced leakage current values.

Study on synergetic effect of potassium pyrophosphate and benzotriazole on chemical mechanical planarization of GLSI low-technology node molybdenum barrier layer

Study on synergetic effect of potassium pyrophosphate and benzotriazole on chemical mechanical planarization of GLSI low-technology node molybdenum barrier layer

Area and power efficient divide-by-32/33 dual-modulus pre-scaler using split-path TSPC with AVLS for frequency divider

Abstract Pre-scalers are electronic circuits used in phase-locked loops to multiply frequencies. This is achieved by dividing the high-frequency signals generated from a voltage-controlled oscillator. The high-frequency operation of pre-scaler circuits leads to significantly higher power consumption. To address this, D flip-flops (D-FF) realized using true-single phase clocking (TSPC) logic. The work suggests incorporating the Adaptive Voltage Level Source (AVLS) circuit with the Dual Modulus Pre-Scaler (DMPS) circuit to reduce power consumption. In addition to the incorporation of the AVLS circuit, pass transistor logic (PTL) used in the feedback, further minimizes transistors and power. This paper proposes three different designs for divide-by-32/33 DMPS circuit. The proposed-1 design combines regular TSPC-based D-FF with PTL in the feedback and an AVLS circuit, resulting in an average power reduction of 36.5%. The proposed-2 design employs split-path TSPC-based D-FF with logic gates and an AVLS circuit, achieving a power reduction of 46.9%. The proposed-3 design employs split-path TSPC-based D-FF with PTL in the feedback and an AVLS circuit, achieving a significant power reduction of 47.8% compared to the existing DMPS circuit and transistor count by 9.1%. The proposed circuits are realized using a CMOS 180 nm technology node. Cadence Virtuoso and Spectre tools are used. The proposed divide-by-32/33 DMPS circuits also realized in the CMOS 45 nm technology node to verify the functionality in the lower technology node. A power reduction of 46.86% observed when compared to the reference circuit. The proposed designs are both power- and area-efficient, making them promising solutions for minimizing power consumption in pre-scaler circuits.

Review of the Nanoscale FinFET Device for the Applications in Nano-regime

Background:The insatiable need for low-power and high-performance integrated circuit (IC) results in the development of alternative options for metal oxide semiconductor field effect transistor (MOSFET) in the ultra-nanoscale regime. The practical challenge of the device scaling limits the use of MOSFET for future technology nodes. ICs are equipped with billions of transistors whose size must be scaled while increasing performance. As the size of the transistor shrinks for the new technology node, the control of the gate over the channel also reduces, leading to sub-threshold leakage. The non-planar technology is the potential methodology to design the ICs for the future technology nodes. The fin-shaped field effect transistor (FinFET) is the most valuable non-planar technology. High sub-threshold slope, better short channel effect (SCE) control, high current drive strength, low dopant-prompted variations, and decreased power dissipation are the prominent features of FinFET technology.Objective:FinFET is an advanced version of MOSFET in terms of geometrical structure. Therefore, in this review paper, the different geometrical structures, working operations, design challenges, future aspects, and the different configurations of FinFETs are presented. The performance of the different configurations of a 1-bit full adder is evaluated and compared.Methods:An overview of FinFET evolution from the planar MOSFET, along with its architecture supported by the requisite equations, is presented in the paper. Besides this, it also gives an insight into the circuit simulation using the FinFETs for the process voltage temperature (PVT) variations, width quantization, design challenges, and the future of FinFETs. A comparative study of FinFET-based 1-bit full adder using various techniques is done to compute and compare the leakage power, delay, and power delay product (PDP).Results:The full adders using FinFETs show less leakage power and PDP. The AND-OR logicbased hybrid full adder using FinFETs shows the least energy consumption per switching. Fin- FET-based gate diffusion input adder shows a 74 % reduction in dynamic power compared to the full adder using MOSFET technology. The low power FinFET-based full adder shows a 54.16 % reduction in leakage power compared to the MOSFET-based full adder. The results signify the effect of multi-gates in curbing the leakage power dissipation.Conclusion:MOSFET faces the practical challenge of device scaling and SCEs at lower technology nodes. It initiates the multi-gate technology for future system generation. FinFET has the capability to design low-power and high-performance circuits in an ultra-nanoscale regime. The geometrical structure of FinFET plays a key role to improve the performance metrics in an ultrananoscale regime.

TREEHOUSE: A Secure Asset Management Infrastructure for Protecting 3DIC Designs

The push to meet growing user requirements and manufacturing challenges at lower technology nodes have motivated chip designers to adopt non-traditional design techniques. 2.5D/3DIC stacking has gained popularity in recent years since it enables chip manufacturers to integrate complex IPs to meet user demands without incurring design penalties. However, the non-traditional nature of the supply chain also means that additional challenges exist for verification and testing of the manufactured design, making the trust assurance of these designs an extremely challenging proposition. While there have been works focussing on securing 3DIC designs, very few address a completely untrusted supply chain. A robust security countermeasure must address the diverse trust requirements of the IPs in the design and the distributed supply chain requirements while ensuring that the functionality and performance overheads of the IC are not violated. We present TREEHOUSE, a trust assurance solution to counter piracy, reverse-engineering, and counterfeiting attacks. TREEHOUSE uses scan authentication to detect piracy and counterfeiting, scan-and functional-locking to prevent reverse-engineering. We evaluate the efficiency of our proposed scheme on an example 3DIC design. We show that TREEHOUSE incurs less than 1% area and power overheads while incurring less than 1% increase in overall gate count for each layer.

Neural Network-based Fast and Intelligent Signal Integrity Assessment Model for Emerging MWCNT Bundle On-Chip Interconnects in Integrated Circuit

At nanometer technology nodes, the efficient signal integrity and performance assessment of vast on-chip interconnects are crucial and challenging. For a long time, copper (Cu) has been used as an interconnect material in integrated circuits (ICs). However, as heading towards lower technology nodes, Cu is becoming inadequate to satisfy the requirements for high-speed applications due to its physical limitations. To mitigate this issue, a multiwall carbon nanotube bundle (MWCNTB) is proven to be a better replacement for Cu. Hence, the current work innovatively focuses on modeling, analysis, and performance evaluation of MWCNTB interconnects at 32 nm technology nodes using various machine learning (ML) and neural network (NN) based techniques for signal integrity assessment and fast computation of on-chip interconnect design. Based on the results obtained by comparing the different performance parameters, it is envisaged that NN-based ADAM technique leads to the best-suited model. The developed model is fruitful in evaluating the output performance of the system, such as power-delay-product (PDP), performing parametric analysis, and predicting optimum input design parameters of the driver-interconnect-load (DIL) system. This work utilizes HSPICE and Python electronic design automation tools for its implementation.

LCINDEP: a novel technique for leakage reduction in FinFET based circuits

Due to the continuous downsizing of metal oxide semi-conductor field effect transistor devices, power dissipation is one of the vital issues for the integrated circuit design. As a result of voltage scaling at lower technology nodes, threshold voltage decreases which results in increase in leakage current, hence leads to increase in leakage power dissipation. In this paper, a novel low leakage technique called LCINDEP (leakage control input DEPendent) is proposed for nano-scaled circuits. The device characteristics and hence overall performance gets affected due to increased power dissipation. Proposed LCINDEP technique is extensively demonstrated for low power operation and reliability analysis. Various short gate (SG) fin type field effect transistor (FinFET) logic circuits are simulated using LCINDEP technique and comparative analysis is performed with the already available leakage reduction techniques. The proposed LCINDEP technique provides reduced leakage power by 89.71% and 91.92% in LCINDEP SG FinFET NAND and NOR gates respectively with respect to the conventional SG FinFET NAND and NOR gates. Besides this benchmark circuits like ring oscillator and ISCAS-85 C17 show decrease in power dissipation by 24.75% and 35.5% respectively with LCINDEP technique in respect to the conventional FinFET circuits. Reliability analysis in terms of process voltage and temperature variations is performed using Monte Carlo Approach for 5000 samples, which also depicts that proposed LCINDEP technique is more reliable than the available low power techniques. The normalized standard deviations (σ/µ)% is improved by 54.68% and 43.93% for power delay product metric in the proposed technique compared to the conventional one for SG FinFET NAND and NOR gates respectively. All the simulations are performed at 16 nm technology node for FinFET logic devices using predictive technology model multigate based on BSIM-CMG on HSPICE tool.

Performance Evaluation of Datapath designs using FinFET and MOSFET

The VLSI Technology has been progressing significantly and the circuits which consume less power become major concern factor for designing todays ICs for Microprocessors and other various systems components. The Datapath is important part of a system. Adders, multipliers, and shift registers are the major components of data path unit of ALU. Almost all digital circuits and chips are made of MOSFET as the basic switching element. But same MOSFET suffers due to Short Channel Effects (SCEs) when scaled down to nano regime, which has promoted multigate device called FinFET. And this FinFET device overcomes the SCEs at technology nodes. In this paper 28T and 16T MOSFET and FinFET based full adders are designed. Using adders, 4x4 array multiplier is designed using both MOSFET and FinFET technology along with it Serial in Serial out shift register designs. The circuits designed based on MOSFET and FinFET are analyzed in terms of power and delay at various nodes. From the software characterization and analysis, it is understood that FinFET based circuits promise better performance at lower technology nodes like 22nm and 14nm than higher technology nodes in MOSFET like 250nm, 180nm, 90nm and 45nm. Hence FinFET becomes a promising device for future IC technology.

Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, two energy-efficient switching activity minimization techniques have been applied with proposed designs. First technique detects the completion of sensing stage operation known as transition completion detection (TCD) technique. TC signal generated from NAND operation of complementary outputs of sensing stage which minimizes glitches in the complementary outputs of the latch stage. Another clock gating mechanism applied at the latch stage to smoothen the output waveforms Q and \(\overline {Q}\). The proposed and existing designs simulated using 32nm CMOS and 32nm CNTFET technology, indicating that the CNTFET based design reduces power by 45% and 36% respectively in comparison with conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop with transition control detection (TCD-LPSAFF) and Ultra Low Energy Sense Amplifier Flip Flop (ULESAFF) give minimal power delay product (PDP) which is 35.7 × 10− 18 J and 29.6 × 10− 18 J respectively. Also, the effect of process variation has been analyzed at specified corners (FF, TT and SS) in the temperature range of -40∘C to 120 ∘C. The performance of all designs has been validated by functionality testing with variation in load cpacitance, diameter, number of tubes and pitch respectively.

On the design of p-channel step-FinFET at sub-10nm node: A parametric analysis

This paper presents a three dimensional (3-D) statistical simulation study of a 7 nm technology node SOI p-channel step-FinFET and compares with that of a conventional FinFET (c-FinFET). For the first time we have investigated the impact of various dimensional parameters like Gate Length (LG), Fin width (Wfin1 and Wfin2, Wfin = fixed), Fin height (Hfin1 and Hfin2, Hfin = fixed) and Fin-width ratio on the performance of c-FinFET and step-FinFET devices. These FinFET structures have been designed and simulated in Cogenda Visual TCAD under certain boundary conditions and the performance has been analyzed. The electrical parameters such as ON-current (ION), OFF-current (IOFF), Sub-threshold Swing (SS), Drain Induced Barrier Lowering (DIBL), threshold voltage (Vt) roll-off, Transconductance (gm) and Transconductance Generation Factor (TGF) are extracted. It is observed that short channel effects (SCEs) can be controlled by reducing Wfin1, decreasing major fin height (Hfin1) and increasing Gate length (LG) (14 nm to 20 nm). It is noticed that there is a significant improvement in ION/IOFF ratio from 1.01 × 104 to 1.41 × 105 with respect to increased channel length, SS of 76.68 mV/decade to 67.8 mV/decade and excellent DIBL of 55 mV/V in c-FinFET. For the proposed step-FinFET at LG = 16 nm there is improved DIBL of 85 mV/V compared to the c-FinFET, which can be further improved up to 64.63 mV/V by decreasing the Hfin1/Hfin2 ratio (4 to 0.25). The parametric analysis concludes that step-FinFET is more susceptible to SCEs in terms of DIBL, Vt roll-off as compared to the c-FinFET. This work considers LG = 16 nm for analysing the dimensional variation effect on both the devices. In contrast c-FinFET is more preferable than the proposed device at lower technology nodes.

Energy Efficient and Variability Immune Adder Circuits using Short Gate FinFET INDEP Technique at 10nm technology node

ABSTRACT Due to the continuous scaling of MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) devices over the past few decades, power consumption has increased tremendously. To reduce power dissipation at lower technology nodes, digital logic circuits are designed with modern (FinFET) devices. In this paper, FinFET INDEP (input dependent) technique-based short gate (SG) FinFET Adder circuits are proposed at 10 nm technology node. The performance comparison of INDEP technique-based adder circuits is done with the SG FinFET adder circuits. The analysis of adder circuits is performed first in terms of functional verification (transient characteristics) and finally for different performance parameters such as propagation delay, power dissipation and power delay product (PDP). The proposed FinFET INDEP technique proves as one of the best leakage reduction techniques for FinFET adder circuits at lower technology nodes. To test the reliability of the circuits, Monte Carlo analysis is also performed. The PDP is improved by 16.8% and 13.73% in INDEP SG FinFET half adder(HA) and INDEP SG FinFET full adder(FA) at 10 nm technology, respectively, in comparison with the ones without INDEP technique. The Monte Carlo simulation results with 3σ Gaussian distribution at ±10% process, voltage and temperature variations show the improvement in PDP in case of SG INDEP FinFET FA and SG INDEP FinFET HA circuit in comparison to SG FinFET FA and FinFET HA circuit, respectively. Simulation is performed using HSPICE tool at 10 nm process technology node.

Schmitt Trigger Designs Using Domino Logic Style

The advancements in the VLSI regime at lower technology node necessitate robust circuit design. Schmitt trigger design using domino logic style exhibit better hysteresis, higher noise margin, and reduced power consumption while compared to static CMOS Schmitt trigger design. This paper proposes three different Schmitt trigger designs based on domino logic style which produces a stable output with increased robustness against noise. The evaluation of dynamic logic-based Schmitt trigger using only NMOS transistors makes high speed operation feasible with reduced power consumption and increased hysteresis. The design, simulation, and analysis of the circuits are performed using Cadence Virtuoso using GPDK 180 nm technology library.

Effect of back gate biasing in negative capacitance field effect transistor

In this paper, we have studied the effect of back gate bias technique in negative capacitance field effect transistor. In N-NCFET, OFF current decreases and threshold voltage increases with positive back gate bias, while with negative back gate bias, OFF current increases and threshold voltage decreases. This behavior of back gate bias in N-NCFET is quite different as compared to N-MOSFET. The primary reason behind this contradictory behavior is the dependence of internal node voltage (VMOS) on the body terminal of N-NCFET via bulk coupling factor. Further, we have utilized this property to design NCFET based inverter.Various figure of merits like noise margin, delay, static power dissipation and dynamic power dissipation is studied for the designed inverter. The designed inverter with suggested back gate bias shows 16% and 13.9% improved noise margin, and reduced delay performance respectively as compared to conventional NCFET without bias. Also, the power dissipation parameter (static and dynamic) is reduced by 90.1% and 3.8% respectively. We have also seen the effect of channel length scaling in the NCFET, decrement in the channel length improves the gate stack capacitance of NCFET which leads to decrement in OFF current at lower technology node.

An insight into the performance analysis of GAA MOSFET for different dielectrics at cryogenic temperatures

A 60 nm gate length, n-type Gate all around (GAA) metal oxide semiconductor field effect transistor (MOSFET) is simulated at different temperature. The temperature dependent electrical characteristics for various temperature are investigated extensively. The improved gate controllability in lower technology node as well as immunity against short channel effects are thoroughly examined. This paper also includes the analog performance analysis of GAA MOSFET along with the DC performances. The performance matrix of the device for different temperature ranging from 70 K to 800 K were illustrated clearly. Results exhibit that the drain current, transconductance, device gain and transconductance to drain current ratio (gm/Ids) improves when temperature is decreased.

A Scalable Fully-Digital Differential Analog Voltage Comparator

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180[Formula: see text]nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1[Formula: see text]V to 1.8[Formula: see text]V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8[Formula: see text]V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55[Formula: see text]mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is [Formula: see text][Formula: see text]V and [Formula: see text][Formula: see text]V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much.

A Survey on Low Power Design Approaches in Nanoscale Regime

Background: The increased demand for battery operated portable systems boost up the field of low power VLSI design. Integrated circuits are enhancing the performance of the systems in terms of lesser area requirement, higher functionality, and faster response at lower technology nodes. The applied power supply and the threshold voltage of the individual device are scaled down at lower technology node. Scaling of the threshold voltage of the devices raises the issue of leakage current. Objective: Leakage current should be made recessive with the continuous scaling of technology nodes. Methods: Various leakage current mitigation methods had been employed to reduce the leakage current at different abstraction levels. This review paper demonstrates the survey of systematic arrangement of device scaling, leakage power, its causes, and various methods to overcome the leakage current at circuit level design. Results: 3 input NAND (NAND3) gate is designed and simulated at 22 nm technology node on HSPICE tool and analyzed for comparison of different leakage reduction techniques. Conclusion: INDEP approach is the most effective approach to reduce the leakage current and to improve the reliability of the circuits followed by DTCMOS technique as compared to other available techniques.

FinFET based SRAMs in Sub-10nm domain

An exponential rise in transistor count, have increased the power consumption of the modern digital system. Moreover, at lower technology node, the performance of conventional CMOS designs degrades because of the short channel effects (SCEs). In sub-10 ​nm technologies, FinFET devices have good gate control and achieve superior performance than CMOS designs. FinFET devices possess high ION current and improved scalability compared to conventional CMOS. Among numerous double gate (DG) devices, the quasiplanar FinFET structure gained huge attention because of the simple fabrication process [4]. However, FinFET based designs have a major width quantization issue. The width of FinFET device varies only in quanta of silicon fin height (HFIN) [4]. This is a critical issue for ratioed designs like Static Random-Access Memory (SRAMs), where proper sizing of transistors is essential for correct functionality. With process variations, this issue becomes even worse and affect the performance of SRAM cell. The SRAM has a significant performance impact on current nanoelectronics systems. Next-generation devices overcome the short-channel effects (SCE) of CMOS technology and can be used to improve the efficiency of SRAM designs. FinFETs are promising emerging devices, which can improve the performance of SRAM designs at lower technology nodes. This review paper presents different types of SRAM bitcells and memory system architectures. It also discusses the detailed analysis of SRAM bitcells based on various highly explored FinFET devices in sub-10nm domain. The read stability and write ability of SRAM cells are determined using Static Noise Margin (butterfly) and N-curve methods. Moreover, this manuscript presents a benchmarking between the Underlapped FinFET based SRAM and Design Technology Optimized FinFET Based SRAM. In addition to this, Monte Carlo simulations are performed on the SRAM cells to evaluate process variations to determine the robustness of SRAM designs. Simulations were done in HSPICE using 7 ​nm technology.

Cryogenic Analysis of Junctionless Nanowire MOSFET during Underlap in Lower Technology Nodes

This paper presents a cryogenic analysis of Junction less Under lapped Nanowire MOSFETs in lower technology nodes. The temperature dependent analysis is carried out to extract the DC figure of merits (FOMs) of the proposed nanowire MOSFET. The analysis is carried out to investigate the drain current associated with the device at different temperature. Further the analysis is extended with underlap length variation from source, drain and both sides. As the trans conductance plays a vital role in device performance estimation, so the analysis is further extended to calculate the transconductance for all the temperature variation and underlap length variation. With the introduction of gate metal under lapping, the sub-threshold behaviour of the proposed structure under different temperature is carried out extensively.