Low Specific On-resistance Research Articles

Electric Characteristics of 5 kV Novel 4H-SiC "SEMOSFET"

A Novel 4H-SiC SEMOSFET (Static channel Expansion MOSFET) was developed. This SEMOSFET has buried gate in addition to MOS gate. By applying a buried gate voltage of less than built-in potential, its channel can be expanded and low specific on resistance was realized. Developed 4H-SiC SEMOSFET has a high performances, such as high blocking voltage, BV, of 5020V, low specific on-resistance, “RonS of 88mΩcm2 and switching speed of less than 35ns. In all reported FETs with MOS structure, the SEMOSFET has the best trade-off between RonS and BV and the largest figure of merit of 286MW/cm2. Its RonS is about 1/140th that of the theoretical limit of Si MOSFET for this BV.

Electric characteristics of normally-off type 5 kV class 4H-SiC JFET, "SEJEET"

A normally-off type 5.3kV 4H-SiC JFET with low specific on-resistance, called SEJFET (Static Expansion channel JFET), has been fabricated. Its normally-off operation was realized by a thin regrown epitaxial channel layer and using the buried p+ regions as a gate in addition to the top p+ regions. The achieved blocking voltage is the highest class BV among the reported SiC JFET. In a 5.3kV 4H-SiC SEJFET, the lowest specific on resistance of 69mΩcm2. Furthermore, the highest current capability among SiC JFET of 3.3A is achieved. In all reported FETs, the SEJFET has the best trade-off between RonS and blocking voltage (BV), which is about 1/230th lower than theoretical limit of a Si FET. Furthermore, the figure of merit (BV2/RonS) is 407MW/cm2, and this value is the highest among reported normally off SiC FETs.

Temperature dependence of On-state characteristics, and Switching characteristics of 5 kV class 4H-SiC SEJFET

A normally-off type 5kV class 4H-SiC JFET with low specific on-resistance, called SEJFET (Static Expansion channel JFET), has been fabricated. Its normally-off operation is realized at the temperature from RT to 600K. A very fast switching time of the 4H-SiC SEJFET are realized. The turn-on time at RT is 20ns and the turn-off time at RT is 47ns. In this SEJFET, temperature dependences of the output characteristics and transfer characteristics are evaluated. Its specific on-resistance has a large positive temperature dependence, and its transconductance has a large negative temperature dependence.

Optimization of a very cost-effective high voltage p-channel transistor implemented in a standard twin-tub CMOS technology

This paper discusses the optimization and fabrication of a high voltage p-channel extended drain MOSFET (ED-pMOSFET) using standard low cost 2.5 μm twin-tub CMOS technology for digital applications, with only one extra processing step. The ED-pMOSFET transistor has been optimized using 2D simulators attending both specific on-resistance and breakdown voltage. Extended drain ED-pMOSFET transistors with low specific on-resistance (active area) R on = 6.0 mΩ cm 2 (at V G = −5 V) and breakdown voltage of 36 V have been implemented demonstrating competitive performance values with other p-channel devices previously reported in more sophisticated technologies. The proposed device along with n-channel LDMOS high voltage devices and the standard low voltage CMOS devices, constitute a full smart power CMOS technology that can reach breakdown voltages up to 50 V and currents up to 1 A.

6A, 1kV 4H-SiC Normally-Off Trenched-and-Implanted Vertical JFETs

This paper presents the design, fabrication and characterization of 4H-SiC trenched-and- implanted vertical JFETs (TI-VJFETs) (1). The design of TI-VJFETs with active areas of 9.38 ×10 -2 mm 2 and 2.03mm 2 and different vertical channel openings is presented based on a blocking layer of 9.4 μm, doped to n=7x10 15 cm -3 . Highly vertical channel defined by trench etching and angled implantation of Al makes it possible to accurately control the vertical channel dimension, resulting in TI-VJFETs with very low specific on-resistance. The TI-VJFET technology developed under this work is believed to be advantageous in comparison to other reported VJFET technologies because (a) it eliminates the need for epitaxial regrowth in middle of the device fabrication (2-5), (b) only one mask requires critical alignment throughout device fabrication, and (c) it provides intrinsically a much lower specific on-resistance due to the elimination of internal lateral JFET gates. Successful applications of the technologies to the development of single-cell TI-VJFETs with power level of 6A -1,000V are reported.

A High Voltage (1,750V) and High Current Gain (β=24.8) 4H-SiC Bipolar Junction Transistor using a Thin (12 μm) Drift layer

This paper reports the first, near theoretical limit breakdown voltage (1,750V) 4H-SiC BJTs with both high DC current gain(24.8) and low specific on-resistance (8.4m Ω·cm 2 at 50A/cm 2 and 12m Ω·cm 2 at 356A/cm 2 ) based on a drift layer of only 12 μm, doped to 8.5x10 15 cm -3 . The high performance is achieved through the use of an optimum single-step junction termination extension (JTE), Al-free base Ohmic contact and wet-oxygen low-temperature re-oxidation annealing. Detailed processing conditions are reported. Room temperature and high temperature current- voltage characteristics are also reported.

3.6 m cm2, 1726 V 4H-SiC normally-off trenched-and-implanted vertical JFETs and circuit applications

A normally-off 4H-SiC trenched-and-implanted vertical JFET (TI-VJFET) with a low specific on-resistance has been demonstrated. The low specific on-resistance (R on―sp ) of 3.6 mQ cm 2 is achieved for a blocking voltage (V bl ) up to 1726 V by eliminating the internal lateral JFET gates. The TI-VJFET technology developed is advantageous in comparison to other reported VJFET technologies because it eliminates the need for epitaxial regrowth in the middle of device fabrication, only one mask requires critical alignment throughout device fabrication, and it provides intrinsically a much lower specific on-resistance owing to the elimination of internal lateral JFET gates. The V 2 bl/R on―sp value of 827 MW/cm 2 for the TI-VJFET substantially surpasses all past records of both unipolar and bipolar SiC power switches. Multi-cell TI-VJFETs have been packaged and tested in an inductively loaded half-bridge inverter. Switching characteristics are reported. A 50 A Darlington transistor has also been developed using the TI-VJFET switches and results are given.

High-density trench gate DMOSFETs with trench contact structure

A novel process technique for fabricating trench gate DMOSFETs using the two-step trench technique and trench contact structure is realised to obtain higher cell density and lower on-resistance. Using this process technique, a remarkably increased trench gate DMOSFET with a cell pitch of 1.6 µm and a channel density of 130 Mcell/in2 are obtained. The fabricated device has a low specific on-resistance of 0.28 mΩ · cm2 with a blocking voltage of 43 V, which is about 23 % lower than that of the device fabricated by the previous method.

High channel density, 20 A 4H-SiC ACCUFET with R onsp =15 mΩ-cm 2

Planar gate 4H-SiC ACCUFETs have been designed, fabricated and characterised, and the highest reported current (>20 A) for this type of device was achieved. A novel channel design to maximise the channel density was implemented. A low specific on-resistance of 15 mΩ-cm2 was obtained on a 9 mm2 device using newly developed N2O anneals on gate oxides. The threshold voltage decreases from 1.5 to 0.9 V, and the extracted channel mobility increases from 18 to 33.6 cm2/V-s as the operating temperature is increased from 30 to 200°C.

Very high density trench gate power MOSFET usingsimplified four-mask process

A new and simplified process for fabricating a high density n-channel trench gate power MOSFET using four mask layers and a sidewall spacer technique is proposed. Use of this process has enabled a remarkably increased high density (100 Mcell/in2) trench MOSFET with a cell pitch of 2.5 µm to be realised. Furthermore, the p-base, n+-source, and trench gate regions were formed by the same mask layer, which made it possible to reduce the number of processing steps. The fabricated device had a low specific on-resistance of 0.7 mΩcm2 with a breakdown voltage of 46 V.

Step-controlled epitaxy of SiC: High-quality homoepitaxial growth

Abstract Chemical vapor deposition (CVD) of silicon carbide (SiC) on off-oriented SiC{0001} substrates (step-controlled epitaxy) is reviewed. In step-controlled epitaxy, surface steps on off-oriented SiC{0001} substrates serve as a template which forces the replication of substrate polytype in the epilayer, and thereby homoepitaxy is realized. High quality of SiC epilayers has been elucidated through optical and electrical characterization. The background doping level could be reduced down to less than 1 × 10 14 cm −3 , and a high electron mobility of 851 cm 2 V −1 s −1 was obtained. Excellent doping controllability over a wide range has been achieved by in-situ doping of a nitrogen donor and an aluminum acceptor. High-voltage (greater than 1 kV) Schottky barrier diodes with low specific on-resistances (less than 5 mωcm −2 ) have been demonstrated by utilizing high-quality epilayers.

High Voltage Silicon Carbide Devices

ABSTRACTProgress made in the development of high performance power rectifiers and switches from silicon carbide are reviewed with emphasis on approaching the 100-fold reduction in the specific on-resistance of the drift region when compared with silicon devices with the same breakdown voltage. The highlights are: (a) Recently completed measurements of impact ionization coefficients in SiC indicate an even higher Baliga's figure of merit than projected earlier. (b) The commonly reported negative temperature co-efficient for breakdown voltage in SiC devices has been shown to arise at defects, allaying concerns that this may be intrinsic to the material. (c) Based upon fundamental considerations, it has been found that Schottky rectifiers offer superior on-state voltage drop than P-i-N rectifiers for reverse blocking voltages below 3000 volts. (d) Nearly ideal breakdown voltage has been experimentally obtained for Schottky diodes using an argon implanted edge termination. (e) Planar ion-implanted junctions have been successfully fabricated using oxide as a mask with high breakdown voltage and low leakage currents by using a filed plate edge termination. (f) High inversion layer mobility has been experimentally demonstrated on both 6H and 4H-SiC by using a deposited oxide layer as gate dielectric. (g) A novel, high-voltage, normally-off, accumulation-channel, MOSFET has been proposed and demonstrated with 50x lower specific on-resistance than silicon devices in spite of using logic-level gate drive voltages. These results indicate that SiC based power devices could become commercially viable in the 21st century if cost barriers can be overcome.

Thin-film quasi-SOI power MOSFET fabricated by reversed silicon wafer direct bonding

A quasi-SOI power MOSFET has been fabricated by reversed silicon wafer direct bonding. In this power MOSFET, the buried oxide under the channel and source regions is removed and the channel region is directly connected to the source body contact electrode to reduce the base resistance of the parasitic npn bipolar transistor. The quasi-SOI power MOSFET can suppress the parasitic bipolar action and shows lower specific on-resistance than that of the conventional SOI power MOSFET. The fabricated chip level quasi-SOI power MOSFET shows the specific on-resistance of 86 m/spl Omega//spl middot/mm/sup 2/ and on-state breakdown voltage of 30 V.

A smart power process in “direct-bonded” silicon on insulator with 150 V VDMOS, CMOS and bipolar transistors

Silicon direct bonding (SDB) has been used to produce silicon-on-insulator (SOI) substrates for dielectrically isolated power devices. The up-drain VDMOS transistors give a low specific on-resistance and allow multiple isolated outputs. The CMOS devices have down to 2 μm drawn channel lengths, here used in a channelless sea of gates semicustom array. The vertical NPN and lateral PNP transistors show characteristics comparable to those of a 60 V bipolar process and make advanced analogue functions possible. The presented process allows fabrication of a 2 A half-bridge circuit with integrated drivers and logic functions.

Optimally scaled low-voltage vertical power MOSFETs for high-frequency power conversion

The systematic optimization of low-voltage silicon power MOSFET technology is described. It is shown that device scaling using advanced fabrication technologies can result in nearly optimal performance from low-voltage silicon power MOSFETs. The details discussed include: (1) system impact; (2) unit cell optimization; (3) device and process modeling; (4) fabrication technology development; and (5) performance results. The device technologies optimized include 30-, 50-, and 100-V vertical power DMOSFETs with optimally scaled gate polysilicon and source/drain contacts. Devices with the lowest specific on-resistance, the lowest specific input capacitance, and improved high-frequency switching performance have been fabricated with excellent wafer yield. This is the first successful demonstration of device scaling and its impact on performance of high-voltage and smart-power technologies.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High voltage power MOSFETs with a trench-gate structure

A two-dimensional numerical analysis has been performed to evaluate the performance of high voltage power MOSFETs with a trench gate structure (UMOSFETs). Such UMOSFETs, utilizing a closely-space vertical trench gate structure, allow a near-ideal doping concentration in the drift region, thus resulting in a very low on-resistance. An optimal design of UMOSFETs for a blocking voltage of 500 V is shown to be a 12 μm unit cell with the lowest specific on-resistance of 49.7 mΩ-cm 2, which is lower than that of the state-of-the art DMOSFET by a factor of 1.75. Designed experimental devices of high voltage UMOSFETs have obtained a very low specific on-resistance of 54 mΩ-cm 2. This is the first time that high voltage power UMOSFETs were analyzed theoretically and consistently demonstrated experimentally.

Numerical and experimental comparison of 60 V vertical double-diffused MOSFETs and MOSFETs with a trench-gate structure

In this paper, a numerical analysis has been performed to evaluate the relative performance of DMOS and UMOS power FETs based on a two-dimensional analytical approach. For the DMOS design, the circular cell was used to approximate the commonly used hexagon cell. An optimal design with the lowest on-resistance of 0.78 mΩ-cm 2 has been identified. For the UMOSFETs with 2 μm trench depth, an optimal design with the lowest on-resistance was identified to be 6 μm cell size with a specific on-resistance of 0.36 mΩ-cm 2. UMOSFET with 4 μm trench depth shows a higher on-resistance of 0.46 mΩ-cm 2 due to a thicker (1000 Å) trench oxide required for 60 V breakdown. Devices of DMOSFET, shallow-trench UMOSFET and deep-trench UMOSFET have been fabricated. Experimental data verified the modeling results: shallow-trench UMOSFET has the lowest specific on-resistance and DMOSFET has the highest specific on-resistance. For high frequency switching applications (> MHz), gate drive loss becomes significant. Both UMOSFETs have similar RC product which is smaller than that of DMOSFET. This translates into the lower power loss (switching plus conduction) for UMOSFETs.