Numerical and experimental comparison of 60 V vertical double-diffused MOSFETs and MOSFETs with a trench-gate structure

Abstract

In this paper, a numerical analysis has been performed to evaluate the relative performance of DMOS and UMOS power FETs based on a two-dimensional analytical approach. For the DMOS design, the circular cell was used to approximate the commonly used hexagon cell. An optimal design with the lowest on-resistance of 0.78 mΩ-cm 2 has been identified. For the UMOSFETs with 2 μm trench depth, an optimal design with the lowest on-resistance was identified to be 6 μm cell size with a specific on-resistance of 0.36 mΩ-cm 2. UMOSFET with 4 μm trench depth shows a higher on-resistance of 0.46 mΩ-cm 2 due to a thicker (1000 Å) trench oxide required for 60 V breakdown. Devices of DMOSFET, shallow-trench UMOSFET and deep-trench UMOSFET have been fabricated. Experimental data verified the modeling results: shallow-trench UMOSFET has the lowest specific on-resistance and DMOSFET has the highest specific on-resistance. For high frequency switching applications (> MHz), gate drive loss becomes significant. Both UMOSFETs have similar RC product which is smaller than that of DMOSFET. This translates into the lower power loss (switching plus conduction) for UMOSFETs.