Low Specific On-resistance Research Articles

Design of Ga2O3 Trench Gate MOSFET Devices with Dielectric Pillars

Abstract In this study, a β-Ga2O3 U-groove gate metal-oxide-semiconductor field-effect transistor (UMOSFET) with a high breakdown voltage (BV) is proposed. Through TCAD simulation, both forward and reverse electrical characteristics are comprehensively investigated. The integration of traps within the current blocking layer (CBL) is suggested to enable effective current blocking. Furthermore, to optimize the BV, the introduction of oxide dielectric pillars on either side of the drift layer is implemented to enhance the potential distribution during breakdown. The forward and reverse electrical characteristics of the device at different temperatures are also investigated. Additionally, by conducting simulation optimizations of different doping concentrations in the drift layer, CBL layer thickness, and trap concentrations, notable achievements are realized, which include a high BV of 865.2 V, low threshold voltage of 2.587 V, and low specific ON-resistance of 19.2 mΩ·cm2. This study presents a novel structural design to foster the potential application and development of Ga2O3 electronic devices.

Ultra-wide Bandgap AlGaN Channel HEMTs for Portable Power Electronics Applications

AlGaN channel (Eg>3.4 eV) is the most effective method for enhancing the breakdown field of the group III-nitride based HEMTs. This work demonstrates the potential of AlGaN double channel HEMTs on Silicon carbide substrate. The device DC characteristics are investigated using numerical simulator by using drift-diffusion transport model. The AlGaN double channel HEMTs enhances the total 2DEG density due to double potential well and shows better current driving capability (IDS) of 0.714 A/mm, transconductance (gm) of 116 mS/mm, and low specific ON-resistance (Ron) of 3.262 Ω.mm. The AlGaN double channel HEMT on Silicon carbide substrate exhibited 680 V blocking voltage (VBR) and gate field plate HEMT shows 532 V. The effective reduction in electric field at the gate edge is the major source for elevated breakdown voltage in field plate HEMTs. The superior DC characteristics indicates the proposed wide bandgap channel HEMT is suitable device for future portable power converters.

Ga2O3 fin field-effect transistors with on-axis (100)-plane gate sidewalls fabricated on Ga2O3 (010) substrates

Ga2O3 fin field-effect transistors (FinFETs) were fabricated on β-Ga2O3 (010) substrates, which had on-axis (100)-plane gate sidewalls treated by nitrogen radical irradiation. The typical FinFET with a fin width (W fin) of 400 nm demonstrated decent on-state device characteristics such as a low specific on-resistance of 6.9 mΩcm2, a high drain current on/off ratio of over 109, and a subthreshold slope of 82 mV/decade. The threshold voltage (V th) of the FinFETs increased with decreasing W fin, and enhancement-mode operation with V th > 0 V was achieved for W fin < 800 nm.

1.2 kV SiC MOSFET with Low Specific ON-Resistance and High Immunity to Parasitic Turn-On

With the capability to switch at high speed, there are important concerns about Parasitic Turn-On (PTO) when using SiC MOSFETs in switching applications with fundamental half-bridge configuration [1]. In this work, we present 1200V SiC planar MOSFETs with low specific ON-resistance (Rsp), fast switching characteristics and high immunity to PTO. The PTO immunity is verified by experimental comparison to several commercially available SiC MOSFETs.

High growth rate metal organic chemical vapor deposition grown Ga2O3 (010) Schottky diodes

We report on the growth of Si-doped homoepitaxial β-Ga2O3 thin films on (010) Ga2O3 substrates via metal-organic chemical vapor deposition (MOCVD) utilizing triethylgallium (TEGa) and trimethylgallium (TMGa) precursors. The epitaxial growth achieved an impressive 9.5 μm thickness at 3 μm/h using TMGa, a significant advance in material growth for electronic device fabrication. This paper systematically studies the Schottky barrier diodes fabricated on the three MOCVD-grown films, each exhibiting variations in the epilayer thickness, doping levels, and growth rates. The diode from the 2 μm thick Ga2O3 epilayer with TEGa precursor demonstrates promising forward current densities, the lowest specific on-resistance, and the lowest ideality factor, endorsing TEGa’s potential for MOCVD growth. Conversely, the diode from the 9.5 μm thick Ga2O3 layer with TMGa precursor exhibits excellent characteristics in terms of lowest leakage current, highest on-off ratio, and highest reverse breakdown voltage of −510 V without any electric field management, emphasizing TMGa’s suitability for achieving high growth rates in Ga2O3 epilayers for vertical power electronic devices.

Electrical performance and reliability analysis of vertical gallium nitride Schottky barrier diodes with dual-ion implanted edge termination

In this study, a gallium nitride (GaN) substrate and its 15 μm epitaxial layer were entirely grown using hydride vapor phase epitaxy (HVPE). To enhance the breakdown voltage (VBR) of vertical GaN-on-GaN Schottky Barrier Diodes (SBDs), a dual ion co-implantation of carbon and helium was used to create the edge termination. The resulting devices exhibited low turn-on voltage of 0.55 V, high Ion/Ioff of approximately 109, and low specific on-resistance of 1.93 mΩ·cm2. With the ion implantation edge termination, the devices achieved a maximum VBR of 1575 V, with an average improvement of 126%. These devices demonstrated a high figure of merit (FOM) of 1.28 GW/cm2 and showed excellent reliability during pulse stress testing.

On the improved RF performance of step field plate LDMOS transistor

This paper presents an analysis of the Step Field Plate Laterally Diffused Metal Oxide Semiconductor (SFP LDMOS) structure for improved high power and RF performance. The proposed structure is cost-effective, CMOS integrable, and has a high power figure of merit (FoM) due to its high off-state breakdown voltage (BVDS,off) and low specific on-resistance (Rsp). Significant improvement in frequency behavior is observed, as demonstrated by the flatter trans-conductance (gm), 12.5x lower gate-to-drain capacitance (Cgd), 2.5x lower gate-to-source capacitance (Cgs), and lower output conductance (gds). Single tone and double tone analyses are performed on an RF PA circuit implemented in TCAD. Results show ∼5 dBm higher output power (Pout), ∼6 dB higher power gain, and 46% higher drain efficiency (η), which are attributed to ∼1.9x lower drain-to-source capacitance (Cds) and ∼15 dBm lower magnitude of third-order intermodulation distortion due to lower third order derivative of drain current (ID). The paper also explains the device physics behind these observations.

Novel high-voltage GaN CAVET with high threshold voltage and low reverse conduction loss

A novel GaN current-aperture vertical electron transistor (CAVET) with an energy band pinning (EBP) structure (EBP-CAVET) is proposed and investigated by simulations. The EBP-CAVET is featured with hybrid contacts on the p-GaN layer, locally having Ohmic contact combined with Schottky gate metals in the longitudinal direction. The Ohmic contact is shorted to the source electrode and the Schottky gate metals are shorted to the gate electrode. The conduction band (Ec) in the gate region is modulated by the alternately arranged contacts. In the Ohmic contact region, Ec remains a fixed value, which acts as an energy band pinning and suppresses the variation of the Ec in the gate region. In the on-state (VGS > 0 V) and blocking-state with high VDS, the EBP structure inhibits the Ec shifting downwards in the gate region to achieve a high threshold voltage (Vth), a low leakage current density (Jdss), and a high breakdown voltage (BV). In the reverse conduction state (VDS < 0 V &VGS ≤ 0 V), the EBP structure suppresses the Ec shifting upwards to achieve a low and independent of gate bias reverse turn-on voltage (VRT). The proposed EBP-CAVET achieves a high Vth of 2.10 V, a VRT of 0.69 V, a low Jdss of 3.1 × 10−11 A/cm2 at VDS = 1000 V, a high BV of 1660 V. Compared with an integrated Schottky barrier diode or fin diode in a field effect transistor (FET), the EBP structure occupies a much smaller chip area. Thus, the EBP-CAVET achieves a low specific ON-resistance (Ron,sp) of 1.19 mΩ cm2 and an extremely high power-figure-of-merit (PFOM) up to 2.32 GW/cm2. Consequently, the proposed structure presents a new design concept and enhances the application potential for GaN CAVET with high Vth and low reverse conduction loss.

Fully-vertical GaN-on-SiC Schottky barrier diode with ultrathin AlGaN buffer layer

In this letter, vertically conductive GaN epilayer on SiC substrate was achieved without the typically used conductive buffer layer. Here, in order to reduce the impacts of band offset of different layers on vertical conductivity and improve the vertical carrier transportation, an ultrathin AlGaN buffer layer was employed to replace the thick conductive buffer layer. Fully-vertical Schottky barrier diode (SBD) based on this vertically conductive epi-stack demonstrated a much lower specific on-resistance of 0.84 mΩ·cm2 with superior thermal stability. Moreover, the SBD also exhibited an on/off ratio of ∼5 × 109 and a nearly unity ideality factor of 1.08. This approach lays the foundation for the heterogeneous integration of GaN/SiC based devices.

Characteristics of β-Ga2O3 MOSFETs on polycrystalline diamond via electrothermal modeling

The integration of polycrystalline diamond (PCD) has been considered as a promising approach for overcoming the thermal management challenges in β-Gallium oxide (β-Ga2O3) metal-oxide-semiconductor field effect transistors (MOSFETs). This study investigates the coupled electrical and thermal characteristics of β-Ga2O3-on-diamond MOSFETs via electrothermal modeling. Results reveal that thicker diamond improves heat transfer efficiency with an optimal value of ∼100 μm by utilizing regions with higher thermal conductivity. The ambient temperature (Tamb) correlates negatively with the device temperature rise (ΔT) due to reduced electrical mobility and current density at elevated temperatures. Excellent electrical performance has been demonstrated for β-Ga2O3 MOSFETs, with a high saturation current density (Id,sat = 42.7 mA/mm) and a low specific on-resistance (RON,sp = 264.8 mΩ·mm2) at 300 K with Vg = −2 V and Vd = 20 V, along with a high on/off ratio (Ion/Ioff ∼ 1011) and a low subthreshold swing (SS = 83.3 mV/dec), making it highly suitable as a power switch. Comparative analysis with devices on other substrates (Si, SiC, and sapphire) highlights the exceptional carrier mobility and heat spreading capability benefited from the diamond substrate, especially at high power levels. Our TCAD-based fully-coupled electrothermal simulations provide comprehensive and accurate insights into the electrical and thermal performance of Ga2O3-based devices, offering guidance for the design and optimization of high-power devices.

(Invited) Gallium Nitride for Vertical Power Devices: Improving Morphology and Unintentional Impurities for Better Devices

While GaN has been researched for many years as a material for light emitting diodes, lasers, high electron mobility transistors, and other devices, further improvements to material purity are still needed to realize the full potential of this material for vertical device applications. To achieve high quality, high purity GaN for power devices, our research employs ammonia-assisted molecular beam epitaxy (NH3-MBE) and plasma-assisted molecular beam epitaxy (PA-MBE). Past studies of fast growth rates (more than 1 μm/hr) and ultra-low impurity incorporation revealed that both PAMBE and NH3-MBE can achieve low net doping levels, and NH3-MBE as low as 1x1015 cm-3.1 However, This work also indicated that impurity incorporation increased with increasing growth rate.Recent research efforts have focused on further improvements to morphology and unintentional dopants in NH3-MBE-grown homoepitaxial layers with fast growth rates. By optimizing growth conditions for faster growth rates and using indium as a surfactant, devices with drift layers up to 10 μm thick were grown. These layers exhibited smooth surface morphology as seen in AFM scans with RMS surface roughness as low as 0.21 nm for a 2x2 μm2 scan area.2 Adding the In surfactant also led to reduced incorporation of unintentional Si impurities in UID films as shown by SIMS depth profiles for GaN films grown with and without In. The extremely low impurity levels were further confirmed by CV measurements which indicated that the net doping density in the UID GaN layers decreased from 2x1016 cm-3 to 5x1015 cm-3 with the addition of the In surfactant.2 Based on these UID levels and the theoretical critical electric field of GaN (3 MV/cm), drift layers up to 29.5 μm and 7.4 μm can be depleted with a triangular electric field profile for net donor concentrations of 5x1015 cm-3 and 2x1016 cm-3, respectively. Devices with the same net concentrations with drift regions 3 μm thick can hold voltages of 854 V and 717 V, respectively.Based on the previously described studies of low-impurity GaN at different growth rates, we developed vertical p-n GaN power devices grown by NH3 MBE.3 These p-n diodes contained a 0.25 µm n+ region, 4 µm n- region with 3x1015 cm-3 unintentional carriers, 0.4 µm p+ region and 10nm p++ capping layer to improve the ohmic anode contact. The circular diodes were fabricated with Pd/Pt anode contacts and Ti/Au cathode contacts. Device diameters were between 80 and 100 µm. The devices featured a 15 µm field plate made from Ti/Au contacts on top of an Al2O3/Si3N4 dielectric stack.The diodes exhibited outstanding forward J-V behavior with a low specific on-resistance (Ron,sp) of 0.28 mΩ-cm2 and a minimum ideality factor of 1.36, which are among the best achieved among similar homoepitaxial GaN p-n diodes.3-5 The best diodes also exhibited a breakdown voltage of > 1 kV (equipment limit 1 kV). The reverse-voltage properties indicate that punch-through was achieved with a peak electric field (EC) >2.6 MV/cm, as confirmed by Silvaco simulations (Fig. 7). The combination of >1 kV breakdown voltage and on-resistance of 0.28 mΩ-cm2 represents one of the best performances of the p-n GaN diodes, achieved with a significantly thinner drift layer compared to comparable MOCVD GaN p-n diodes with drift layers more than 8 µm. Work is ongoing to develop NH3-MBE p-n diodes with indium surfactant-assisted drift layer growth which shows promise to further improve the surface morphology, reduce leakage, and enhance breakdown performance of the vertical devices.

Morphological and Electrical Characterization of AlGaN/GaN Heterostructures Modified By Atomic Layer Etching

Modern microelectronic components for high-power and high-frequency applications based on III-V compound semiconductors offer high break down voltage (GaN: 5 MV/cm and AlN: 15 MV/cm) at low specific on-resistance. However, it requires reliability and reproducibility of the production processes. Going to higher frequencies (5 GHz and beyond) and more integration in consumer electronics, smaller structure sizes are needed. This is going along with increasing demands on the manufacturing processes like dry etching. The main goal is to reach smaller and high controllable etching rates, going down to single atomic layers, low damage, and minimized surface roughness. Atomic layer etching (ALE) represents a key technology in order to achieve such requirements.An ALE process consists of two independent steps forming a repeatable cycle with a specific etching amount per cycle (EPC). First a surface modification is done by a chemical precursor i.e., adsorbing or oxidizing the surface. The second step is the removal of the modified layer, either physically by low energy non-reactive ion bombardment (Plasma Enhanced ALE [PEALE]) or chemically by a reactive species (Thermal ALE). The two steps are separated by an inert gas purge. This purging grants the removal of the chemistry after the first step, preventing further chemical reaction and transporting the chemical products out of the chamber after the second step.In this study, a PEALE conducted on different tools is used, for gate and contact recess study in a AlGaN/GaN heterostructure to form high electron mobility transistors (HEMT) with reduced ohmic contact resistance and threshold voltages. The results show a reduction of ohmic contact resistance at reduced forming temperatures and a linear dependence of the threshold voltage on gate recess depth. In order to determine the etching rate and roughness, atomic force microscopy (AFM) measurements were performed.The PEALE module is either integrated into a cluster tool consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD) or done in a combined ALD/ALE chamber. This opens the possibility of etching and depositing in-situ, reducing contamination and degradation of the substrate material.By this means, metal insulator semiconductor (MIS)-HEMTS with a recessed gate are studied. The monitoring of the individual processes is achieved by test structures like transfer length method structures (TLM) and metal oxide semiconductor (MOS), which showed the improved electric performance of these devices and may indicate unwanted interface issues, respectively. Additional, pre- and post-treatments could improve the interfaces further. The results will be presented and discussed in terms of ALE process development and optimization.This work was financially supported within the ALEStar project by the government of the Free-state of Saxony and the European Regional Development Fund under grant no. SAB 100402929.

A Novel SiC Trench MOSFET with Self-Aligned N-Type Ion Implantation Technique.

We propose a novel silicon carbide (SiC) self-aligned N-type ion implanted trench MOSFET (NITMOS) device. The maximum electric field in the gate oxide could be effectively reduced to below 3 MV/cm with the introduction of the P-epi layer below the trench. The P-epi layer is partially counter-doped by a self-aligned N-type ion implantation process, resulting in a relatively low specific on-resistance (Ron,sp). The lateral spacing between the trench sidewall and N-implanted region (Wsp) plays a crucial role in determining the performance of the SiC NITMOS device, which is comprehensively studied through the numerical simulation. With the Wsp increasing, the SiC NITMOS device demonstrates a better short-circuit capability owing to the reduced saturation current. The gate-to-drain capacitance (Cgd) and gate-to-drain charge (Qgd) are also investigated. It is observed that both Cgd and Qgd decrease as the Wsp increases, owing to the enhanced screen effect. Compared to the SiC double-trench MOSFET device, the optimal SiC NITMOS device exhibits a 79% reduction in Cgd, a 38% decrease in Qgd, and a 41% reduction in Qgd × Ron,sp. A higher switching speed and a lower switching loss can be achieved using the proposed structure.

Enhancing performance of β-Ga2O3 diodes through a NixO/SiNx/Ga2O3 sandwich structure

In this study, we propose and investigate a novel sandwich structure composed of NixO/SiNx/Ga2O3 for the purpose of enhancing the forward current density and reducing the on-resistance in β-Ga2O3 diodes. The fabricated sandwich Ga2O3 diode demonstrates an impressive forward current density exceeding 1 kA/cm2 under a forward bias of 2 V, surpassing previously reported Ga2O3 Schottky diodes. Furthermore, the sandwich diode exhibits a remarkably low differential specific on-resistance (Ron,sp) of 1.1 mΩ·cm2. These findings present a promising avenue for the design of high-current Ga2O3 power electronics.

Interface charge engineering on an in situ SiNx/AlGaN/GaN platform for normally off GaN MIS-HEMTs with improved breakdown performance

This work adopts interface charge engineering to fabricate normally off metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) on an in situ SiNx/AlGaN/GaN platform using an in situ O3 treatment performed in the atomic layer deposition system. The combination of in situ SiNx passivation and an O3-treated Al2O3/AlGaN gate interface allows the device to provide an excellent breakdown voltage of 1498 V at a low specific on-resistance of 2.02 mΩ cm2. The threshold voltage is increased by 2 V by significantly compensating the net polarization charges by more than five times with O3 treatment as well as reducing the interface traps and improving the high-temperature gate stability. Furthermore, a physical model of fixed charges at the Al2O3/AlGaN interface is established based on dielectric thickness-dependent linear fitting and numerical calculations. The matched device performance and simulated energy band bending elucidate the O3-treated fixed-charge modulation mechanism, providing a practical method for producing normally off GaN MIS-HEMTs.

Novel Vertical Fin-Based NiO/β-Ga2O3 Heterojunction Field-Effect Transistor with a Low Ron,sp

In this paper, a novel vertical fin-based NiO/β-Ga2O3 heterojunction field-effect transistor (Fin-HJFET) is proposed and studied by TCAD. Theoretically high conduction band offset () enables Ga2O3 Fin-HJFET to produce electron confinement effect at certain gate bias voltage. According to the simulation results, this effect makes Ga2O3 Fin-HJFET can not only form surface-conducting fin channels that are not available in conventional fin-based junction field-effect transistor (Fin-JFET) but also have a stronger electron accumulation capability than Ga2O3 vertical FinFET due to the deep potential well, which leads to a lower specific on-resistance (). In addition, Ga2O3 Fin-HJFET inherits the advantages of Ga2O3 FinFET as a vertical normally-off device and has a higher breakdown voltage compared to FinFET without field plates due to the protection of the highly doped NiO layer. Particularly, Fin-HJFET with different heterojunction band alignments are also considered and discussed. At last, the parameter influence and future optimization space of this highly promising device are explored, providing guidance for actual device fabrication and future device improvement.

1 kV GaN-on-Si Quasi-Vertical Schottky Rectifier

This work demonstrates quasi-vertical GaN Schottky barrier diodes (SBDs) on 6-inch Si substrate with a breakdown voltage (BV) over 1 kV, the highest BV reported in vertical GaN-on-Si SBDs to date. The deep mesa inherently in quasi-vertical devices is leveraged to form a self-aligned edge termination, and the mesa sidewall is covered by the p-type nickel oxide (NiO) as a reduced surface field (RESURF) structure. This novel termination enables a parallel-plate junction electric field of 2.8 MV/cm, being close to the material limit for GaN. The device also shows a high on/off ratio of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , low turn-on voltage of 0.5 V, and low specific on-resistance of 1.1 mΩ∙cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Moreover, the device exhibits excellent overvoltage robustness under the continuous 800 V stress in the unclamped inductive switching test. These results show the good promise of the low-cost vertical GaN-on-Si power diodes.

A novel substrate Voltage-assisted RESURF technique in SOI LDMOS with a heavily doped drift region

A novel substrate voltage-assisted (SVA) reduced surface field (RESURF) technique in SOI lateral double-diffused Metal-Oxide-Semiconductor (LDMOS) with a heavily doped drift region is proposed. Without any additional masks and processes, an external control circuit is designed to adaptively control the substrate voltage in the technique. The co-simulation based on TCAD and the circuit is implemented to explore the mechanism of the SVA RESURF technique. In the off-state, a negative bias is applied to the substrate, which induces positive charges to compensate for the heavily doped ionizing acceptors in the drift region. The breakdown voltage is improved and remains at the same level as the conventional RESURF device. In the on-state, a zero bias is applied to the substrate, and heavy doping in the drift region can achieve low specific on-resistance compared to the RESURF device with a lightly doped drift region. As a result, the proposed technique reconstructs the charge balance and the conventional RESURF condition. The simulation results show reduced specific on-resistance, low drain leakage current, large saturation current, high transconductance and cut-off frequency, decreased turn-on/off characteristics and improved FOM and BFOM compared with the conventional RESURF technique. Furthermore, an analytical model is developed to optimize the substrate voltage for the maximum breakdown voltage in the external control circuit design of the proposed technique.

Silicon Carbide Power Devices: Progress and Future Outlook

Silicon Carbide (SiC) power devices have become commercialized and are being adopted for many applications after 40 years of effort to produce large diameter wafers and high performance device structures. This paper provides a historical perspective of the key breakthroughs that were needed to make progress towards this goal. The JBS rectifier concept was a critical innovation required to make SiC power Schottky rectifiers viable. The Baliga-Pair or Cascode concept was an intermediate step to realize a practical SiC power switch in the 1990s. An essential unique innovation created in the 1990s was the shielded planar SiC power MOSFET structure that is now commonly used for commercial products. Shielded trench-gate SiC power MOSFETs were also proposed in the 1990s which led to commercial products in the last 5 years. Although achieving a low specific on-resistance in SiC power MOSFETs was essential at the inception of the technology, its penetration into power electronics applications is now driven by performance metrics for high frequency circuits. Device structural enhancements to improve the high frequency figures-of-merit are described that have led to major strides in performance. This includes the JBSFET concept where a JBS diode is integrated into the MOSFET structure to suppress current flow through the body diode; the SG and BG MOSFET structures which reduce the gate-drain charge; and the OCTFET structure where the gate-drain overlap area is reduced. Future developments in SiC power devices include increasing the blocking voltage rating to expand the applications spectrum. In addition, a SiC monolithic bi-directional switch has been demonstrated to allow implementation of matrix converters; and a SiC monolithic reverse blocking switch has been demonstrated to allow deployment of current source inverters.

GaN/Si Heterojunction VDMOS with High Breakdown Voltage and Low Specific On-Resistance.

A novel VDMOS with the GaN/Si heterojunction (GaN/Si VDMOS) is proposed in this letter to optimize the breakdown voltage (BV) and the specific on-resistance (Ron,sp) by Breakdown Point Transfer (BPT), which transfers the breakdown point from the high-electric-field region to the low-electric-field region and improves the BV compared with conventional Si VDMOS. The results of the TCAD simulation show that the optimized BV of the proposed GaN/Si VDMOS increases from 374 V to 2029 V compared with the conventional Si VDMOS with the same drift region length of 20 μm, and the Ron,sp of 17.2 mΩ·cm2 is lower than 36.5 mΩ·cm2 for the conventional Si VDMOS. Due to the introduction of the GaN/Si heterojunction, the breakdown point is transferred by BPT from the higher-electric-field region with the largest radius of curvature to the low-electric-field region. The interfacial state effects of the GaN/Si are analyzed to guide the fabrication of the GaN/Si heterojunction MOSFETs.