Morphological and Electrical Characterization of AlGaN/GaN Heterostructures Modified By Atomic Layer Etching

Abstract

Modern microelectronic components for high-power and high-frequency applications based on III-V compound semiconductors offer high break down voltage (GaN: 5 MV/cm and AlN: 15 MV/cm) at low specific on-resistance. However, it requires reliability and reproducibility of the production processes. Going to higher frequencies (5 GHz and beyond) and more integration in consumer electronics, smaller structure sizes are needed. This is going along with increasing demands on the manufacturing processes like dry etching. The main goal is to reach smaller and high controllable etching rates, going down to single atomic layers, low damage, and minimized surface roughness. Atomic layer etching (ALE) represents a key technology in order to achieve such requirements.An ALE process consists of two independent steps forming a repeatable cycle with a specific etching amount per cycle (EPC). First a surface modification is done by a chemical precursor i.e., adsorbing or oxidizing the surface. The second step is the removal of the modified layer, either physically by low energy non-reactive ion bombardment (Plasma Enhanced ALE [PEALE]) or chemically by a reactive species (Thermal ALE). The two steps are separated by an inert gas purge. This purging grants the removal of the chemistry after the first step, preventing further chemical reaction and transporting the chemical products out of the chamber after the second step.In this study, a PEALE conducted on different tools is used, for gate and contact recess study in a AlGaN/GaN heterostructure to form high electron mobility transistors (HEMT) with reduced ohmic contact resistance and threshold voltages. The results show a reduction of ohmic contact resistance at reduced forming temperatures and a linear dependence of the threshold voltage on gate recess depth. In order to determine the etching rate and roughness, atomic force microscopy (AFM) measurements were performed.The PEALE module is either integrated into a cluster tool consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD) or done in a combined ALD/ALE chamber. This opens the possibility of etching and depositing in-situ, reducing contamination and degradation of the substrate material.By this means, metal insulator semiconductor (MIS)-HEMTS with a recessed gate are studied. The monitoring of the individual processes is achieved by test structures like transfer length method structures (TLM) and metal oxide semiconductor (MOS), which showed the improved electric performance of these devices and may indicate unwanted interface issues, respectively. Additional, pre- and post-treatments could improve the interfaces further. The results will be presented and discussed in terms of ALE process development and optimization.This work was financially supported within the ALEStar project by the government of the Free-state of Saxony and the European Regional Development Fund under grant no. SAB 100402929.