Low-voltage Operational Amplifier Research Articles

0.8 V bulk-driven operational amplifier

A low-voltage bulk-driven CMOS operational amplifier is proposed in this paper. The inherent small transconductance of the bulk-driven devices is enlarged using a positive feedback, improving also the noise performance. The amplifier is designed using standard 0.18 μm n-well CMOS process. Although the amplifier is optimized for 0.8 V supply voltage, it is also capable to operate under supply voltage of 0.7 V. The amplifier consumes 130 μΑ, performing 56 dB open-loop gain, 154 nV/√Hz input-referred spot noise at 100 kHz, 80 dB CMRR at 100 kHz and IIP3 equal to −4.7 dBV.

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion –94.3 dB with Nyquist input signal frequency.

Low-voltage low-power operational amplifier for SC circuits

A novel class-AB architecture for two-stage operational amplifiers is presented. A set of level-shifters are utilised to generate continuous and stable class-AB behaviour in both the first and the second stage, which enhances the effective values of the slew rates and transcondutances in both stages and thus opamp speed with extraordinary low power.

All low voltage lateral junction scanning tunneling microscope with very high precision and stability

We describe the first lateral junction and fully low voltage scanning tunneling microscope, featuring very high precision, stability, compactness, and image quality (highly oriented pyrolytic graphite atomic resolution images). In its core, the tip and sample each sit on one of two parallel-mounted piezoelectric tube scanners so that the tip-sample gap is regulated along the scanners' pairing direction. The scanner's large lateral deflection provides a large gap regulation range even under low voltages, allowing exclusively using only low voltage (less than +/-15 V) operational amplifiers to precisely implement the coarse (inertial slider) and fine approach, feedback control, and hence the entire electronics. Because the scanners are identical and adjacent, thermal drifts are minimal.

Low-distortion low-voltage operational transconductance amplifier

A new operational transconductance amplifier (OTA) is proposed, which is based on the flipped voltage follower and source degeneration techniques. The OTA is simulated in a standard TSMC 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show that the total harmonic distortion of the proposed OTA is less than 1% up to 0.85 Vp-p.

Low-Voltage CMOS Current Feedback Operational Amplifier and Its Application

A novel low-voltage CMOS current feedback operational amplifier (CFOA) is presented. This realization nearly allows rail-to-rail input/output operations. Also, it provides high driving current capabilities. The CFOA operates at supply voltages of ±0.75 V with a total standby current of 304 µA. The circuit exhibits a bandwidth better than 120 MHz and a current drive capability of ±1 mA. An application of the CFOA to realize a new all-pass filter is given. PSpice simulation results using 0.25 µm CMOS technology parameters for the proposed CFOA and its application are given.

A 0.8-V 0.25-mW Current-Mirror OTA With 160-MHz GBW in 0.18-<formula formulatype="inline"><tex>$\mu{\hbox {m}}$</tex></formula> CMOS

A low-voltage low-power CMOS operational transconductance amplifier (OTA) with near rail-to-rail output swing is presented in this brief. The proposed circuit is based on the current-mirror OTA topology. In addition, several circuit techniques are adopted to enhance the voltage gain. Simulated from a 0.8-V supply voltage, the proposed OTA achieves a 62-dB dc gain and a gain-bandwidth product of 160 MHz while driving a 2-pF load. The OTA is designed in a 0.18-mum CMOS process. The power consumption is 0.25 mW including the common-mode feedback circuit

Quasi Rail-to-Rail Very Low-Voltage OPAMP With a Single pMOS Input Differential Pair

In this brief, a quasi-rail-to-rail low-voltage operational amplifier (VDD-VSS-VDSATP-VDSATN ) is introduced. A common-mode adapter that uses the common-mode voltage present at the common-source node of the available differential pair to accommodate the large common-mode input signal is proposed. The common-mode adapter operates properly at 300 kHz while driving a load capacitor of 15 pF and employs only 95 muW of static power. The amplifier was fabricated in a standard AMI 0.5-mum CMOS process (Vtn=0.7 V and Vtp=-0.9 V) and achieves an IM3 of - 48 dB at 300 kHz for a two-tone input signal of 0.8 Vpk-pk. A 1-V total supply voltage was used

1-V DTMOS-Based Class-AB Operational Amplifier: Implementation and Experimental Results

In this paper, we describe a novel low-voltage class-AB operational amplifier (opamp) based on dynamic threshold voltage MOS transistors (DTMOS). A DTMOS transistor is a device whose gate is tied to its bulk. DTMOS transistor pseudo-pMOS differential input pairs are used for input common-mode range enhancement, followed by a single ended class-AB output. Two versions of the proposed opamp (opamp-A and opamp-B) were fabricated in a standard 0.18-mum CMOS process technology. Measurements under 5 pF and 10 kOmega load conditions gave, for opamp-A, a DC open-loop gain of 50.1 dB, and a unity gain bandwidth (GBW) of 26.2 MHz. A common-mode rejection ratio (CMRR) of 78 dB, and input and output swings of 0.7 V and 0.9 V, respectively, were achieved. Opamp-B has been optimized for biomedical applications, and is implemented to build the analog front-end part of a near-infrared spectroreflectometry (NIRS) receiver of a multi-wavelength wireless brain oxymeter apparatus. A DC open-loop gain of 53 dB, a GBW of 1.3 MHz, and input and output swings of 0.6 V and 0.8 V, respectively, were measured. Opamp-A consumes 550 muW with an input referred noise of 160 nV/radicHz at 1 kHz. Opamp-B consumes only 40 muW and exhibits a lower input referred noise of 107 nV/radicHz at 1 kHz

A free but efficient low-voltage class-AB two-stage operational amplifier

A simple and efficient low-voltage two-stage operational amplifier with Class-AB output stage is introduced. It has a large effective output current boosting factor (/spl sim/50) and close to a factor 2 bandwidth enhancement. This is achieved at the expense of minimum increase in circuit complexity and no additional static power dissipation. Experimental verification of the characteristics of the proposed circuit is provided.

A 0.8 V CMOS amplifier design

A low-voltage operational amplifier design in a standard CMOS process is presented for operation at ±0.4 V. The design incorporates a low voltage level shift current mirror using forward body-biased MOSFETs limited to a maximum of 0.4 V to minimize latchup and hot carrier effects. Some of the measured performances are as follows: 58 dB open-loop gain, 30 kHz bandwidth, 50° phase margin and 80 ?W power dissipation and are in close agreement with the corresponding design and SPICE simulated values.

A new modeling and optimization of gain-boosted cascode amplifier for high-speed and low-voltage applications

Because of limited output swing, the basic structure of a gain-boosted cascode amplifier (GBCA) cannot be used to design a low-voltage operational amplifier. In this paper, we investigate the design of a high-swing GBCA, and find the optimum bandwidth for the boosting or feedback amplifier. This bandwidth eliminates the slow-settling component in the step response, prevents the gain-boosting loop from being unstable, and results in the shortest settling time. Finally, we present a very high-speed and high-swing amplifier suitable for low-voltage applications.

Effects of MOSFET mismatch on the performance of single supply low voltage operational amplifiers

PurposeIn this paper, we study the effect on the performance of a single supply low voltage operational amplifier due to such a mismatch.Design/methodology/approachWe start with a given set of specifications and design a MOSFET based operational amplifier meeting those specifications. We then compute various parameters of the operational amplifier using PSPICE to verify that the amplifier meets the specifications. We create mismatch in three characteristics of differential pair MOSFETs: zero biased threshold voltage (Vth0), channel length (L) and process transconductance parameter (K). The effect of the mismatch on two performance parameters: (a) differential mode gain and (b) output DC voltage is then studied.FindingsThe effects of mismatch in MOSFET characteristics on the performance of single supply low voltage operational amplifiers are studied. Circuit designers can use the results to design operational amplifiers and other analog circuits to minimize the effects of such a mismatch on the performance of their circuits. In some cases, such a mismatch may even be desirable to obtain a desired performance from the circuit.Practical implicationsCircuit designers can use the results to design operational amplifiers and other analog circuits to minimize the effects of such a mismatch on the performance of their circuits.Originality/valueEffect of mismatch of the transistor characteristics on the performance of circuits rarely reported in literature. This study is presented to aid circuit designers in designing circuits with enhanced performance.

Design and comparison of very low-voltage CMOS output stages

This paper analyzes and compares CMOS output stages for very low-voltage operational amplifiers. The analysis was carried out by taking into account output stage performance parameters which also affect the characteristics of the overall amplifier. In particular, three quality factors were defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth, and linearity. Exploiting these new parameters, four output stages were analyzed in detail and compared. Finally, comparison results were validated by simulations.

Low-Voltage Super class AB CMOS OTA cells with very high slew rate and power efficiency

A simple technique to achieve low-voltage power-efficient class AB operational transconductance amplifiers (OTAs) is presented. It is based on the combination of class AB differential input stages and local common-mode feedback (LCMFB) which provides additional dynamic current boosting, increased gain-bandwidth product (GBW), and near-optimal current efficiency. LCMFB is applied to various class AB differential input stages, leading to different class AB OTA topologies. Three OTA realizations based on this technique have been fabricated in a 0.5-/spl mu/m CMOS technology. For an 80-pF load they show enhancement factors of slew rate and GBW of up to 280 and 3.6, respectively, compared to a conventional class A OTA with the same 10-/spl mu/A quiescent currents and /spl plusmn/1-V supply voltages. In addition, the overhead in terms of common-mode input range, output swing, silicon area, noise, and static power consumption, is minimal.

Gm-Extraction for rail-to-rail input stage linearization

Transconductance of rail-to-rail input stages in low-voltage operational amplifiers depends on the presence of a large common mode input signal. Corrections must be implemented in order to correct it. Nevertheless, techniques actually used, based on switching or feedforward, still give relevant deviation from the constant transconductance condition. In this paper we present a new architecture based on extraction and feedback to the gain control, directly of the value of the transconductance of the amplifier to be controlled. This quantity does not contain the signal to be amplified, and thus once fed back, it does not affect the overall stage gain. A ‘reciprocal’ circuit, which performs the 1/x mathematical function, is introduced in order to achieve this extraction. Copyright © 2005 John Wiley & Sons, Ltd.

Digital Calibration for Monotonic Pipelined A/D Converters

The original digital calibration approach for 1 b/stage and 1.5 b/stage pipeline analog-digital converters produces missing or nonmonotonic digital codes with the device and circuit impairments typical of modern deep submicrometer CMOS technologies. Two digital calibration algorithms are introduced to improve pipeline performance when using low-voltage low-gain nonlinear operational amplifiers and high random dc offset voltage comparators. The first technique computes calibration coefficients for each stage at actual transition points of the residue characteristic to assure converter monotonicity in the presence of random comparator offset voltages. The second augments a conventional pipelined architecture with an input-dependent level-shifting stage and additional digital calibration circuitry to achieve high differential and integral linearity with low-gain nonlinear operational amplifiers.

Exploiting the high-frequency performance of low-voltage low-power SC filters

This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided.

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications

The authors present a new fully differential operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. Owing to the class AB operation in the second stage, slew limiting occurs only in the first stage, resulting in low power dissipation for switched-capacitor circuits. It employs a novel hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling. A design procedure for the minimum settling time of the proposed OTA is described. To demonstrate the efficiency of the proposed OTA and its compensation method three design examples are also provided.

Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Power consumption is one of the main design challenges in very-low-voltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in low-voltage fast-settling operational amplifiers for switched-capacitor applications are discussed. These techniques include the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-μm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers.