Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Abstract

Power consumption is one of the main design challenges in very-low-voltage high-speed analog integrated circuits. In this paper, different techniques to reduce the power consumption in low-voltage fast-settling operational amplifiers for switched-capacitor applications are discussed. These techniques include the cascode compensation, a new class-A/AB output stage and a novel dynamic allocation of settling time parameters. Design considerations for a 1.5-V very-low-power operational amplifier merging these techniques are addressed. HSPICE simulation results of the circuit in a 0.25-μm CMOS process confirm the effectiveness of the approaches to considerably reduce the power consumption of high-speed operational amplifiers.