Low Thermal Budget Process Research Articles

Impact of UV annealing on the hole effective mobility in SnO pFET

Using ultraviolet (UV) annealing through wide energy bandgap HfO2/SiO2 gate dielectric, nanosheet SnO pFET achieved hole effective mobility (µeff) from 55 cm2/V-s at low hole density (Qh) to 13.38 cm2/V-s at 5 × 1012 cm-2 Qh, compared to that of 9.03 cm2/V-s at 5 × 1012 cm-2 Qh for SnO device without UV annealing. This is the highest µeff among oxide semiconductor pFETs at high Qh, which is required to realize low-power high-density monolithic 3D CMOS logic. This requires excellent surface roughness, good uniformity and free-from grain boundaries that is beyond the thermally-annealed poly-Si. Excellent on-current/off-current (ION/IOFF) value of 1.05 × 105 were measured simultaneously in the UV-annealed SnO pFET, which is due to the ultra-thin 8 nm thick SnO nanosheet channel to pinch off the channel leakage. From X-ray photoelectron spectroscopy (XPS) analysis, the 48% µeff improvement by UV irradiation is due to increased Sn2+ and decreased Sn0. Such high µeff at high Qh, large ION/IOFF, smooth surface, good uniformity and low thermal budget process are the enabling technologies for monolithic 3D CMOS.

Self-powered photodetector based on 1D TiO2-3D CdS mixed dimensional heterostructure fabricated at low temperature

Solution processed photodetectors have garnered great attention in applications such as, machine vision perception, neuromorphic computing and opto-electronic memory storage. Though, such photodetectors offer several advantages such as ease of fabrication, high scalability, low thermal budget and low-cost processing, multi-modal functionality etc. however, they suffer from the major drawback of inferior device performance −as low responsivity and slow rise time, particularly due to the intrinsic poor crystallinity of the photoactive material. In this work, we demonstrate a solution processed photodetector with impressive performance at comparatively low processing temperatures (<150 °C) based on the mixed dimensional heterostructure configuration of 1D TiO2 nanorods and 3D CdS nanoflowers. TiO2 nanorods have been synthesized by hydrothermal technique, whereas their CdS sensitization is done by chemical bath deposition. Low cost carbon paste is used as electrode instead of conventional non-economic noble metal electrodes. X-ray diffraction studies validated excellent crystallinity of the photoactive material even under low temperature processing condition. The type-II Heterojunction (TiO2 and CdS) configuration photodetector shows efficient response at zero bias, thus yielding a self-powered device. The detector shows response in UV and visible region, with excellent responsivity of 110 mA/W (5 V), 563 µA/W (0 V) and a quicker rise time of 81 ms. Albeit the simple fabrication scheme and low processing temperatures, the detector exhibited promising figures-of-merit, which aids in fabrication of novel solution processed photodetectors.

Impact of nanosecond laser annealing on vacancies in electroplated Cu films studied by monoenergetic positron beams

Positron annihilation was used to probe vacancy-type defects in electrodeposited Cu films after nanosecond pulse laser annealing. For the as-deposited Cu film, we identified the coexistence of two different vacancy-type defects, vacancy clusters (such as V16) and monovacancy-type defects, coupled with impurities. An enlargement in the vacancy size was observed after the laser annealing process. The size of these defects was estimated to be close to V30, and such defects could not be formed by conventional furnace annealing. After furnace annealing at 400 °C, the size of the larger vacancy clusters decreased, but that of the smaller vacancies increased. The observed change in the sizes of vacancies is considered to be related to interactions between vacancies and impurities. The depth profile of the defects varied by changing the laser energy density and the number of laser shots. The impact of laser annealing on the vacancy-type defects was observed even after furnace annealing at 800 °C. Because the presence of point defects in electroplated Cu directly correlates with electromigration and grain growth, the ability of laser annealing to introduce large vacancy clusters in the localized region shows the potential of nanosecond laser annealing as a low-thermal budget process tool for back-end-of-line materials.

Pulsed Rapid Thermal Annealing as a Low Thermal Budget Semiconductor Fabrication Process

Thermal annealing is required in the fabrication of many semiconductor devices. A proper annealing condition, e.g., temperature, atmosphere, and time, can improve the device performance, e.g., by reducing defect densities in bulk films and at interfaces. In addition, the annealing step can generate new structures in previously deposited thin films for various new functions. However, when the annealing condition is improper, e.g., the temperature is too high or the annealing time is too long, the device performance can deteriorate or dysfunction due to damage to the composing material, structure, or even the substrate. The thermal budget is critical in the thermal annealing step.Pulsed rapid thermal annealing (PRTA), which exposes the sample to repeated cycles of short-period heating and cooling, is a low thermal budget process. In this presentation, the principle of PRTA is presented. Examples of using PRTA in the crystallization of amorphous silicon on the glass substrate to polycrystalline thin films for thin film transistors (TFTs) and solar cells, improving high-k gate dielectric properties for MOS capacitors and solid state incandescent light emitting devices (SSI-LEDs), and preparation of nanocrystals embedded high-k structure for nonvolatile memories will be shown (1-4). Limitations of PRTA and possible improvements will be discussed. Kuo and P. M. Kozlowski, Appl. Phys. Lett., 69(8), 1092-1094 (1996).Kuo, C.-H. Lin, and M. Zhu, IEEE Photovoltaic Specialist Conf. PVSC 35, 3698-3701 (2010).Y. Kuo and C. H. Lin, ECS 237th Meeting # 130648, May 10-15, 2020.Y. Kuo, ECS 227th Meeting # 47306 (1333), May 24-28, 2015.

(Invited) Improvements in Thermal Budget and Film Properties Using Low Pressure Cure Technology for Advanced 3D Integration Packaging

3D advanced integration with Fan-Out Wafer-Level Packaging (FOWLP) and Fan-Out Panel Level Packaging (FOPLP) offers multiple benefits: heterogenous chip design and stacking, increased interconnect density, and improved performance. However, it also brings new requirements for more compact form factors, low thermal budget materials and processing, and lower cost. The materials, process, and fabrication of heterogenous integration on redistribution layers (RDLs) consisting of metal and polymer dielectrics have become important enablers of the move to advanced packaging applications. To achieve the low-stress and low-cost benefits required by advanced integrated devices, thermal budgets must be reduced throughout the heterogenous integration flow -- including the dielectric curing step, which demands the use of low temperature processing and reduced cure times.In this presentation, the low temperature and low pressure thermal polymerization of dielectric polyimides used for redistribution layers (RDLs) is reviewed. Specifically, this presentation illustrates the significant impact of the low pressure cure process in reducing temperature (20° to 50° lower) and cure times (up to a 50% reduction) while providing better mechanical (elongation%, tensile strength, Young’s modulus), thermal (TG, Td 1%, Td 5%), and electrical (Dk, Df, dielectric breakdown strength - DBS) properties for different types of dielectric polyimides, including the Fujifilm LTC-9300 series, the Asahi BL-300 series, and the Toray LT-8300 and PW-1500 series. The post-curing polymerization ratio (FT-IR) and film stress were studied and are described. Finally, a proposed mechanism for the described dielectric polyimides’ polymerization under reduced pressure is discussed.Ongoing developments in design, materials, process and fabrication for FOWLP and FOPLP devices continue to drive progress in 3D heterogenous integration. This study of thermal processing of dielectric polyimides at low pressure and shorter time demonstrates a promising technique to improve overall process flow by reducing thermal budget, stress, and cost.

Improving the High-Temperature Gate Bias Instabilities by a Low Thermal Budget Gate-First Process in p-GaN Gate HEMTs

In this study, we report a low ohmic contact resistance process on a 650 V E-mode p-GaN gate HEMT structure. An amorphous silicon (a-Si) assisted layer was inserted in between the ohmic contact and GaN. The fabricated device exhibits a lower contact resistance of about 0.6 Ω-mm after annealing at 550 °C. In addition, the threshold voltage shifting of the device was reduced from -0.85 V to -0.74 V after applying a high gate bias stress at 150 °C for 10-2 s. The measured time to failure (TTF) of the device shows that a low thermal budget process can improve the device's reliability. A 100-fold improvement in HTGB TTF was clearly demonstrated. The study shows a viable method for CMOS-compatible GaN power device fabrication.

An Emerging Local Annealing Method for Simultaneous Crystallization and Activation in Xtacking 3-D NAND Flash

The high thermal budget of three-dimensional NAND Flash (3D NAND Flash) is the key issue limiting the increase in vertical integration. The main purpose of this article is to design a local and high temperature annealing function to reduce the thermal budget and gain a high activation rate without diffusion at a target depth to improve the performance of 3D NAND Flash devices by laser annealing with green wavelength. The method of nanosecond pulse laser annealing (ns-PLA) for amorphous silicon (a-Si) crystallization and activation has been proven, and this method has the benefits of a low thermal budget and controllable heating. According to previous experiments, one of the important results is that ns-PLA with high energy can provide a high temperature that reaches the melting point of a-Si and obtain a deep and monocrystal-like silicon channel through liquid phase crystallization in 3D NAND applications and obtain a higher activation rate. These results cast emerging light on low thermal budget processes based on ns-PLA in 3D NAND flash for future architecture such as Xtacking architecture, and have significant ramifications for impurity activation rates and reducing channel leakages.

Impact of the Low Temperature Ohmic Contact Process on DC and Forward Gate Bias Stress Operation of GaN HEMT Devices

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1\Omega ~\cdot $ </tex-math></inline-formula> mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied.

Low-thermal-budget n-type ohmic contacts for ultrathin Si/Ge superlattice materials

Thermal budget is a vital element of Si-based superlattice material processing. In this work, a novel n-type ohmic contact scheme with a low thermal budget process is developed by combining high-dose ion implantation and low-temperature alloying techniques. The optimized specific contact resistivity (ρ c) is reduced to 6.18 × 10−3 Ω cm2 at a low thermal budget of 400 °C, and this is a result of the efficient low-temperature electrical activation of amorphous substances. It is indicated that both the high doping concentration and the formation of a NiSi(Ge) alloy phase contribute to the linear ohmic contact behavior. The ohmic contact resistance dependence on processing temperature is further revealed by a detailed Ni/Si(Ge)alloying model. A minimum ρ c of 2.51 × 10−4 Ω cm2 is achieved at a thermal budget of 450 °C, which is related to the high bonding intensity at the metal–semiconductor interface. Note that this technique is compatible with standard Si-based CMOS process flows and can be applied in high-performance insulated-gate field-effect transistor (IGFET) fabrication. Furthermore, it is verified that the Si/Ge superlattice structures in our IGFETs can serve as an efficient potential barrier to constrain electrons.

Atomic tailoring of low-thermal-budget and nearly wake-up-free ferroelectric Hf0.5Zr0.5O2 nanoscale thin films by atomic layer annealing

In recent years, ferroelectric hafnium zirconium oxide (Hf0.5Zr0.5O2, HZO) has emerged as apromising candidate for nonvolatile memory and energy storage devices. A low thermal budget technique for achieving sub-10 nm HZO thin films with pronounced ferroelectricity is highly demanded for ferroelectric applications such asadvanced semiconductor technology nodes. In this paper, the atomic layer annealing (ALA) technique, which is thein situHe/Ar plasma treatment incorporated into the atomic layer deposition cycle, is demonstrated to achieve the transformation from amorphous to orthorhombic phase in sub-10 nm HZO layers without the need of any high-temperature post annealing. As compared with the ALA process conducted on each ZrO2monolayer, the ALA treatment performed on each HfO2monolayer is much preferred in terms of superior crystallinity and ferroelectric properties of the HZO thin films. Hence a high remanent polarization together with a nearly wake-up-free property are accomplished in the HZO layer. The study demonstrates ALA is an effective technique to realize the atomic tailoring ofcrystalline quality and ferroelectric/dielectric characteristics of nanoscale thin films at a low temperature, which is very favorable in a variety of applications including biomedical, wearable, and nanoelectronic devices, in which a low thermal budget process is required.

Sol-Gel Composites-Based Flexible and Transparent Amorphous Indium Gallium Zinc Oxide Thin-Film Synaptic Transistors for Wearable Intelligent Electronics

In this study, we propose the fabrication of sol-gel composite-based flexible and transparent synaptic transistors on polyimide (PI) substrates. Because a low thermal budget process is essential for the implementation of high-performance synaptic transistors on flexible PI substrates, microwave annealing (MWA) as a heat treatment process suitable for thermally vulnerable substrates was employed and compared to conventional thermal annealing (CTA). In addition, a solution-processed wide-bandgap amorphous In-Ga-Zn (2:1:1) oxide (a-IGZO) channel, an organic polymer chitosan electrolyte-based electric double layer (EDL), and a high-k Ta2O5 thin-film dielectric layer were applied to achieve high flexibility and transparency. The essential synaptic plasticity of the flexible and transparent synaptic transistors fabricated with the MWA process was demonstrated by single spike, paired-pulse facilitation, multi-spike facilitation excitatory post-synaptic current (EPSC), and three-cycle evaluation of potentiation and depression behaviors. Furthermore, we verified the mechanical robustness of the fabricated device through repeated bending tests and demonstrated that the electrical properties were stably maintained. As a result, the proposed sol-gel composite-based synaptic transistors are expected to serve as transparent and flexible intelligent electronic devices capable of stable neural operation.

High-Performance Oxide-Based p-n Heterojunctions Integrating p-SnOx and n-InGaZnO.

The fabrication of oxide-based p-n heterojunctions that exhibit high rectification performance has been difficult to realize using standard manufacturing techniques that feature mild vacuum requirements, low thermal budget processing, and scalability. Critical bottlenecks in the fabrication of these heterojunctions include the narrow processing window of p-type oxides and the charge-blocking performance across the metallurgical junction required for achieving low reverse current and hence high rectification behavior. The overarching goal of the present study is to demonstrate a simple processing route to fabricate oxide-based p-n heterojunctions that demonstrate high on/off rectification behavior, a low saturation current, and a small turn-on voltage. For this study, room-temperature sputter-deposited p-SnOx and n-InGaZnO (IGZO) films were chosen. SnOx is a promising p-type oxide material due to its monocationic system that limits complexities related to processing and properties, compared to other multicationic oxide materials. For the n-type oxide, IGZO is selected due to the knowledge that postprocessing annealing critically reduces the defect and trap densities in IGZO to ensure minimal interfacial recombination and high charge-blocking performance in the heterojunctions. The resulting oxide p-n heterojunction exhibits a high rectification ratio greater than 103 at ±3 V, a low saturation current of ∼2 × 10-10 A, and a small turn-on voltage of ∼0.5 V. In addition, the demonstrated oxide p-n heterojunctions exhibit excellent stability over time in air due to the p-SnOx with completed reaction annealing in air and the reduced trap density in n-IGZO.

Improved resistive switching characteristics of Ag/Al:HfO x /ITO/PET ReRAM for flexible electronics application

The Al-doped HfO x flexible resistive random access memory (ReRAM) device with Ag top electrode (TE) is fabricated on indium tin oxide (ITO) coated polyethylene terephthalate (PET) with low thermal budget process. The oxygen vacancies created by Al doping may assist Ag inclusion to create/rupture the filament at lower operating voltages (V SET ≈ 0.46 V and V RESET ≈ −0.93 V) and SET/RESET currents (I SET ≈ 2 × 10−5 A and I RESET ≈ 8 × 10−5 A). The Ag/Al:HfO x /ITO/PET ReRAM exhibits highly stable resistive switching (RS) behaviour with lower switching power (P SET ≈ 9.2 µW and P RESET ≈ 74.4 µW). The stable switching parameters like SET/RESET voltages, resistances in high resistance states (HRS) and low resistance states (LRS) are observed even at higher temperature (100 °C) and in flexible condition (i.e. 5 mm dia). The current conduction mechanism in HRS is dominated by space charge limited conduction whereas LRS is not completely Ohmic in nature. The RS mechanism has been explained by the formation of the combined effect of Ag atoms and oxygen vacancies. Considering the improved performance of the ReRAM device fabricated at low-temperature process, it may provide a promising candidate for the low power flexible electronics applications.

Wafer scale epitaxial germanium on silicon (0 0 1) using pulsed laser annealing

Pulsed Nd:YAG (1064 nm) laser was used to crystallize amorphous germanium thin-films on silicon (001) wafer to get epitaxial Ge. Film thickness and laser fluence played a crucial role. Thicker films (≥300 nm) are polycrystalline while thinner films are epitaxial. Rocking curve measurements show improvement in crystallinity with increase in laser fluence. The full 2-in. laser crystallized wafer has omega scan of 0.20° and implied threading dislocation density of 6 × 108 cm−2. Hence, a fast, cost-effective, and low thermal budget process is used to achieve epitaxial Ge on Si for large area applications.

Investigation of Hydrogen Effect on Ferroelectricity of Atomic Layer Deposited Hf0.5Zr0.5O2 Thin Film

Ferroelectrics have retrieved great interest since the discovery of a ferroelectric phase in HfO2.1 Especially, ferroelectric Hf0.5Zr0.5O2 (HZO) thin films have studied for application as a non-volatile memory and field-effect transistor, due to their high scalability and compatibility with CMOS process.2 In our previous work, we have achieved a low thermal budget process (400 °C) by controlling the tensile stress from the TiN electrode during the annealing process.3 Moreover, the TiN electrode can act as a barrier layer against hydrogen diffusion, therefore, the HZO films using the TiN electrodes can prevent degradation of the ferroelectric properties from hydrogen incorporation. However, during the deposition of HZO film using atomic layer deposition (ALD), the choice of oxygen source can affect the residue in the deposited film. When hydrogen-related substances are used as the oxygen source, the ferroelectric properties can be altered by the residues remaining in the HZO film.In this study, we adopted various oxygen sources such as H2O, deuterium oxide (D2O), and O3, for the investigation of hydrogen effect on the ferroelectric properties of the ALD-HZO films. The HZO films were deposited on the TiN bottom electrode by ALD using Hf[N(CH3)2]4 (TDMA-Hf) and Zr[N(CH3)2]4 (TDMA-Zr) as the precursors of Hf and Zr, while H2O, D2O, or O3 as the oxidant. After the TiN top electrode was deposited, rapid thermal annealing was done, and metal-insulator-metal capacitors were fabricated using a Pd/Au hard mask and wet etch process.The HZO films exhibited the formation of a non-centrosymmetric orthorhombic phase which is origin of the ferroelectricity, without consideration for the oxygen sources.4 However, it was confirmed that the ferroelectricity of the HZO film deposited with the oxygen source including hydrogen such as H2O and D2O, was degraded due to the more incorporation with hydrogen. As a result, the ferroelectric polarization of H2O-, and D2O-based HZO was lower than that of O3-based HZO. Simultaneously, the H2O- and D2O-based HZO exhibited higher leakage current than that of O3-based HZO. The results strongly suggest that the suppression of hydrogen incorporation is important to apply ALD-HZO films for next-generation memory application.This work is supported by the National Research Foundation of Korea (NRF) grant (No. NRF-2019R1F1A1059972), Brain Pool Program (No. 2019H1D3A2A01101691), and the Fostering Global Talents for Innovative Growth Program (No. P0008750). 1 T. S. Böscke, et al., Appl. Phys. Lett. 99, 102903 (2011). 2 S.J. Kim, et al., Appl. Phys. Lett. 113, 182903 (2018). 3 S.J. Kim, et al., Appl. Phys. Lett. 111, 242901 (2017). 4 S.J. Kim, et al., JOM 71, 246 (2019). Figure 1

High infrared reflectance modulation in VO2 films synthesized on glass and ITO coated glass substrates using atmospheric oxidation of vanadium

Vanadium Dioxide (VO2) is a strongly correlated material, which exhibits insulator to metal transition at ~68 C along with large resistivity and infrared optical reflectance modulation. In this work, we use atmospheric pressure thermal oxidation of Vanadium to synthesize VO2 films on glass and ITO coated glass substrates. With the optimized short oxidation durations of 2 min and 4 min, the synthesized VO2 film shows high optical reflectance switching in long-wavelength infrared on glass substrates and mid-wavelength infrared on ITO coated glass substrates, respectively. Peak reflectance switching values of ~76% and ~79% are obtained on the respective substrates, which are among the highest reported values. Using the reflectance data, we extract VO2 complex refractive index in infrared wavelengths, in both the insulating and metallic phases. The extracted refractive index shows good agreement with VO2 synthesized using other methods. This demonstration of high optical reflectance switching in VO2 thin films, grown on low cost glass and ITO coated glass substrates, using a simple low thermal budget process will aid in enhancing VO2 applications in the optical domain.

Adhesive Wafer Bonding Using Ultra-Thin Spray-Coated BCB Layers

Permanent adhesive wafer bonding is a mature technology as it provides the advantages of a low thermal budget process and is less sensitive to the quality of the bonding surfaces. One of the most used materials for this process is Benzocyclobutene (BCB). Due to its usage the material was further developed for bonding applications. In this work we report the fabrication of ultrathin BCB bonding layers (down to 25 nm thickness) by means of spray coating. The advantages of such bonding layers are both technical (e.g. no substrates shift due to adhesive layer flow during bond process) or and economical (significantly lower material consumption compared to spin coating). The fabrication and characterization of such bonding layers is presented and bonding results are presented.

Single-Grain Gate-All-Around Si Nanowire FET Using Low-Thermal-Budget Processes for Monolithic Three-Dimensional Integrated Circuits.

We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.

A Comprehensive Study on the Effect of TiN Top and Bottom Electrodes on Atomic Layer Deposited Ferroelectric Hf0.5Zr0.5O2 Thin Films.

The discovery of ferroelectricity in HfO2-based materials in 2011 provided new research directions and opportunities. In particular, for atomic layer deposited Hf0.5Zr0.5O2 (HZO) films, it is possible to obtain homogenous thin films with satisfactory ferroelectric properties at a low thermal budget process. Based on experiment demonstrations over the past 10 years, it is well known that HZO films show excellent ferroelectricity when sandwiched between TiN top and bottom electrodes. This work reports a comprehensive study on the effect of TiN top and bottom electrodes on the ferroelectric properties of HZO thin films (10 nm). Investigations showed that during HZO crystallization, the TiN bottom electrode promoted ferroelectric phase formation (by oxygen scavenging) and the TiN top electrode inhibited non-ferroelectric phase formation (by stress-induced crystallization). In addition, it was confirmed that the TiN top and bottom electrodes acted as a barrier layer to hydrogen diffusion into the HZO thin film during annealing in a hydrogen-containing atmosphere. These features make the TiN electrodes a useful strategy for improving and preserving the ferroelectric properties of HZO thin films for next-generation memory applications.

Low thermal budget high-k/metal surface gate for buried donor-based devices

Atomic precision advanced manufacturing (APAM) offers creation of donor devices in an atomically thin layer doped beyond the solid solubility limit, enabling unique device physics. This presents an opportunity to use APAM as a pathfinding platform to investigate digital electronics at the atomic limit. Scaling to smaller transistors is increasingly difficult and expensive, necessitating the investigation of alternative fabrication paths that extend to the atomic scale. APAM donor devices can be created using a scanning tunneling microscope (STM). However, these devices are not currently compatible with industry standard fabrication processes. There exists a tradeoff between low thermal budget (LT) processes to limit dopant diffusion and high thermal budget (HT) processes to grow defect-free layers of epitaxial Si and gate oxide. To this end, we have developed an LT epitaxial Si cap and LT deposited Al2O3 gate oxide integrated with an atomically precise single-electron transistor (SET) that we use as an electrometer to characterize the quality of the gate stack. The surface-gated SET exhibits the expected Coulomb blockade behavior. However, the gate’s leverage over the SET is limited by defects in the layers above the SET, including interfaces between the Si and oxide, and structural and chemical defects in the Si cap. We propose a more sophisticated gate stack and process flow that is predicted to improve performance in future atomic precision devices.