Abstract
We introduce a single-grain gate-all-around (GAA) Si nanowire (NW) FET using the location-controlled-grain technique and several innovative low-thermal budget processes, including green nanosecond laser crystallization, far-infrared laser annealing, and hybrid laser-assisted salicidation, that keep the substrate temperature (Tsub) lower than 400 °C for monolithic three-dimensional integrated circuits (3D-ICs). The detailed process verification of a low-defect GAA nanowire and electrical characteristics were investigated in this article. The GAA Si NW FETs, which were intentionally fabricated within the controlled Si grain, exhibit a steeper subthreshold swing (S.S.) of about 65 mV/dec., higher driving currents of 327 µA/µm (n-type) and 297 µA/µm (p-type) @ Vth ± 0.8 V, and higher Ion/Ioff (>105 @|Vd| = 1 V) and have a narrower electrical property distribution. In addition, the proposed Si NW FETs with a GAA structure were found to be less sensitive to Vth roll-off and S.S. degradation compared to the omega(Ω)-gate Si FETs. It enables ultrahigh-density sequentially stackable integrated circuits with superior performance and low power consumption for future mobile and neuromorphic applications.
Highlights
To catch up to Moore’s law, and to benefit from a faster computing speed and economical chip, there are two approaches [1,2] followed and adopted in the semiconductor industry: one is “more Moore” which means keep downsizing the dimension of the transistor using a new device structure or non-silicon materials; the other is “more than Moore” which introduces a heterogeneous integration concept in the out-of-plane direction
The key of fabricating such a sequentially 3D stackable transistor or further integrated circuit lies in developing low-thermal budget processes, which means the substrate temperature should not be higher than 400 ◦C to keep the metal interconnect reliable and to be compatible with back end of line (BEOL) processes [16,17]
To remove the surface defects caused by the laser process and to improve the overall channel uniformity, the chemical mechanical polish (CMP) was introduced to thin the thick and large-grain polycrystalline Si film down to below 50 nm (Figure 1b)
Summary
To catch up to Moore’s law, and to benefit from a faster computing speed and economical chip, there are two approaches [1,2] followed and adopted in the semiconductor industry: one is “more Moore” which means keep downsizing the dimension of the transistor using a new device structure or non-silicon materials; the other is “more than Moore” which introduces a heterogeneous integration concept in the out-of-plane direction The latter is known as three-dimensional integrated circuits (3D-ICs). There has been several researches aiming to develop sequentially 3D stackable techniques using a layer transfer method, namely SmartCutTM with semiconductoron-insulator wafers, e.g., SOI, GOI, or III-V-OI [11,12] This technique could provide better channel quality, it still needs to face the potential high-temperature annealing process of 3D stackable transistor manufacturing. The main task is to develop a thin and high-crystallinity channel and further low-thermal budget processes for sequentially 3D stackable devices with high performance and low variability
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