Low Thermal Budget Process Research Articles

Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors

A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (/spl les/550/spl deg/C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH/sub 3/ plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step is not needed. A field effect mobility of 46 cm/sup 2//V-s, ON/OFF current ratio of over 10/sup 7/, and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.

Local atomic structure and electrical properties of nitrided SiSiO 2 interfaces produced by low-temperature plasma processing and rapid thermal annealing, and explained by ab-initio quantum chemistry calculations

This paper discusses the effectiveness of nitrogen (N-) atom incorporation at SiSiO 2 interfaces in improving device reliability. N-atoms are introduced by a low thermal budget process that includes: (i) a 300°C plasma-assisted oxidation/nitridation; (ii) a 300°C plasma-assisted deposition of the dielectric layer; and (iii) a 900°C post-deposition anneal, either as a separate 30 s rapid thermal annealing (RTA) step, or during dopant activation of the gate electrode. The amount of incorporated-N has been varied at the monolayer range by using N 2 O O 2 mixtures for the oxidation step, and has been measured by Auger electron spectroscopy (AES), secondary ion mass spectrometry (SIMS), and optical second harmonic generation (OSHG). A model, based on ab-initio calculations, is used to explain the role of N-atoms in improving device reliability, e.g. in reducing H-atom induced generation of positively-charged defects, the so-called anomalous positive charge (APC).

Influence of a silicon cap on SiGe passivation by anodic oxidation

ABSTRACTWe applied electrochemical oxidation as a low thermal budget process for the passivation of thin SiGe epilayers on Si substrate and compared the results with those obtained on thermally oxidized layers. The use of a thin silicon cap on the SiGe layer reduces the electrochemical corrosion with dissolution of Ge during oxidation and leads to a higher amount of GeO2 in the oxidized SiGe layer than anodic oxidation without a Si cap. The protected SiGe layer shows a slight Ge enrichment at the interface which is different from the behavior of the non-protected SiGe layer. The highest Ge pile-up is achieved by the thermally oxidized samples where the oxide layer is formed by nearly pure SiO2. Using photoluminescence spectroscopy we showed that the passivation and quality of the interface is best if no Ge enrichment occurs. The results suggest that electrochemical oxidation of SiGe layers is preferable to high temperature processing.

Rapid thermal chemical vapor deposited oxides on N-type 6H-silicon carbide

The electrical characteristics of oxides deposited on nitrogen doped N-type 6H-silicon carbide using rapid thermal chemical vapor deposition are reported. The gases used in the deposition process were silane (diluted with argon), and nitrous oxide. The oxide was found to have an interface state density of 7/spl times/10/sup 11/ cm/sup -2/eV/sup -1/ and a low effective charge density of 1.1/spl times/10/sup 11/ cm/sup -2/. The deposited oxide is compared with oxide grown thermally on N-type 6H-silicon carbide by wet oxidation. The quality of the deposited oxide is found to be comparable to the quality of the thermal oxide. An excellent low thermal budget process to obtain good oxides on N-type 6H-silicon carbide has thus been demonstrated for the first time. >

Crystallization of Pb(Zr,Ti)O3 films prepared by radio frequency magnetron sputtering with a stoichiometric oxide target

Highly oriented and ferroelectric Pb(Zr,Ti)O3 (or PZT) thin films were obtained by radio frequency magnetron sputtering of a stoichiometric oxide target (Zr/Ti ratio of 53/47). No excess lead was used either during sputtering or during postdeposition annealing. Films deposited at 200 °C or below crystallize into a perovskite phase upon receiving anneal treatment at 590 °C or above. The annealing study, carried out using a conventional furnace, also revealed that the perovskite formation is completed during the first 5 min of annealing. The annealed films are highly (100) oriented on (111)-Pt coated oxidized Si substrates. Maximum polarization of 36 μC/cm2, remanent polarization of 20 μC/cm2, and coercive field of 22 kV/cm were obtained with excellent fatigue resistance. This suggests that the low thermal-budget process (i.e., low-temperature deposition and short-time anneal in a conventional furnace) with a stoichiometric oxide target may be appropriate as a reliable, simple, and economical method of preparing PZT films. Depositions at 500 °C or higher, however, resulted in TixOy or ZrTiO4 films, suggesting that lead was significantly lost during deposition.

Needs of Low Thermal Budget Processing in SiGe Technology

Needs of Low Thermal Budget Processing in SiGe Technology

N-Channel Mos Transistors below 0.5 μm with Ultra-Shallow Channels formed by Low Temperature Selective Silicon Epitaxy

AbstractIn this paper, we present an application of ultra high Vacuum Rapid Thermal Chemical Vapor Deposition (UHV-RTCVD) to MOSFET channel engineering. MOSFETs were fabricated on ultra-thin (200 Å), moderately doped (l×1017 - 6×1018 cm−3) p-type epitaxial layers selectively grown in active areas defined by standard LOCOS isolation. The selective epitaxy was achieved using a novel Si2H6Cl2/B2H6 process at 800°C and at a total pressure under 30 mtorr. Low thermal budget processing techniques were emphasized to minimize spread in the channel doping profile. Threshold voltages below 0.6 V were obtained. Transistors with effective channel lengths of 0.45 μm exhibit subthreshold slopes from 78 to 92 mV/decade determined by the epitaxial channel doping density. We have found that by using ultra-thin channels, expected transconductance degradation at high channel doping densities can be minimized. Furthermore, ultra-thin channels help reduce the sensitivity of the threshold voltage on substrate bias. The results show that low temperature selective silicon epitaxy can be used to form ultra-shallow channel doping profiles that can enhance the performance of MOSFETs in the deep submicron regime.

Low Thermal Budget Processing Of Organic Dielectrics

AbstractLow dielectric constant organic materials are ideal for use as interconnect dielectrics forintegrated circuits. As compared to silicon dioxide, organic dielectrics with K <3.84 reducepower dissipation, crosstilk and RC delays in interconnects. Curing is essential afterdeposition of these materials to initiate polymerization reactions and form films of desirableelectrical properties. For high performance and reliability, low thermal budget processing isa necessity. Rapid isothermal processing (RIP) based on the use of dual spectral sources isa potential technique to lower the thermal budget. In this paper, we demonstrate the role ofphotoeffects in the curing of polyimide films (K∼2.6) using a rapid isothermal processor witha dual spectral source (Tungsten Halogen and vacuum ultra violet (VUV) lamps) as a sourceof optical and thermal energy. Lamp configurations that allowed a greater availability of ultraviolet and vacuum ultra violet photons on the film to initiate physical and chemical processesallowed a lower curing temperature to achieve the same level of immidization. Furthermore, these samples also gave the lowest leakage current and film stress. Therefore, the rapidheating and cooling features of rapid isothermal processing in conjunction with lowerprocessing temperature through the use of high energy photons to enhance surface reactionsgive superior film properties

Integrated Processing of Silicon Oxynitride Alloy Dielectrics by Plasma-Assisted Oxidation, Chemical Vapor Deposition, and On-Line Rapid Thermal Annealing

AbstractThin film dielectrics have been prepared in a cluster processing system with chambers for plasma-assisted, rapid-thermal processing, and on-line Auger electron spectroscopy (AES). A low-thermal budget process for the formation of homogeneous silicon oxynitride (OXN) alloy films is presented. This Na2-based plasma-CVD process has (i) increased process latitude for the formation of N-rich alloys, and (ii) results in lower bonded-H concentrations, in comparison with a similar NH3-based process. Gate dielectric formation consists of (i) a 300°C plasma-assisted oxidation for removal of residual hydrocarbons, and formation of an Si-SiO2 interface protected by ∼0.5-0.6 nm of oxide, (ii) a 300°C plasma-assisted CVD of oxynitride films from N2O, N2, and SiH4, and (iii) a 30 s, 900°C post-deposition rapid-thermal anneal in an ambient that contains sufficient oxygen to prevent decomposition of the Si/SiO2 interface. On-line AES and off-line infrared (IR) spectroscopy have been used to characterize chemical bonding, showing that the deposited films are pseudo-binary alloys lying on a join-line from SiO2 and Si3N4 in a ternary composition diagram. Electrical characterization of MOS capacitors, consisting of O-OXN-O structures, using C-V techniques is discussed.

Integration of plasma cleaning and light-assisted CVD for the passivation of III–V semiconductor surfaces

Passivation of III-V semiconductor surfaces and especially the GaAs surface has been studied for over two decades without significant breakthrought. However III-V device performances are still often limited by surface properties. In particular field effect behaviour in GaAs has been impossible to obtain due to the Fermi level pinning at the surface of this material. This paper presents an integrated sequence of low thermal budget processes to provide contamination control at the GaAs surface leading to very promising field effect on GaAs. In-situ surface cleaning using a Distributed Electron Cyclotron Resonance Microwave plasma (DECR MMP) has been integrated with a thin dielectric film deposition facility using light assisted CVD technics. Photoluminescence results carried out on GaAs surfaces have demonstrated that exposure to a hydrogen plasma induces lower recombination rates on these surfaces. Bulk diffusion of hydrogen during this process can be controlled and eliminated using an integrated Rapid Thermal Annealing (RTA). Finally, in-situ encapsulation by a dielectric allows one to stabilize the electronic properties of the surface for passivation applications. A silicon nitride film deposited by a direct UV photolysis deposition process has been developed for this study and is presented here.

Rapid Thermal Annealing in Advanced Silicon Bipolar Technology

A rapid thermal anneal (RTA) process has been investigated in detail for the applications of emitter diffusion and anneals in an advanced double‐polysilicon bipolar process. The significance of thin oxide at the emitter‐polysilicon‐to‐silicon interface for a low thermal budget process using RTA is presented in this paper. A change in wafer loading temperature from 400 to 600°C at emitter polysilicon deposition increased the emitter resistance from 30 to 700 Ω for emitter diffusion using RTA at 1025°C for 30 s. In contrast, emitter resistance of wafers that went through diffusion in a furnace at 1000°C for 15 min was insensitive to the wafer loading temperature at emitter polysilicon deposition. Such a large increase in emitter resistance for the RTA process is attributed to oxidation of the silicon surface during wafer loading at elevated temperatures at the emitter polysilicon deposition step. The interaction of RTA and subsequent heat cycles on the heavily doped polysilicon sheet resistance is discussed in the second section. Sheet resistance of arsenic‐ and boron‐doped polysilicon increased by more than 50% when the wafers were annealed in a furnace at 800°C after the RTA emitter diffusion at 1050°C for 30 min. The reverse annealing was explained by the dopant deactivation from (i) segregation to grain boundaries and (ii) return to equilibrium concentration from supersaturation and dopant precipitation. The bipolar process employs an RTA heat cycle at 850°C for 10 s to transform the C49 phase of to the low resistivity C54 phase. The short RTA cycle resulted in superior silicide morphology and low contact resistance at the interface between and n+ polysilicon layers compared to a furnace anneal process.

Improvement of the SiO2/Si interface of metal-oxide-semiconductor devices using gate dielectrics formed by NF3-aided oxidation and N2O post-annealing

With the increasing requirement for ultrathin gate dielectrics in advanced metal-oxide-semiconductor structures, a low thermal budget process to grow thin dielectric film is vital, while at the same time maintaining the good interface quality and thin film reliability. In this article, thermal nitridation of fluorinated oxide in N2O ambient was investigated. While fluorinated oxides provide a lower thin film stress and better interface than conventional oxides, an excess amount of fluorine in the starting oxide has an adverse effect on the high field stability. For N2O-nitrided oxide, high temperature and prolonged nitridation time reduce the interface state generation ΔDit resulting from avalanche electron injection at the expense of increasing the flatband voltage shift ΔVfb. The electrical properties are strongly process dependent. The best operating window of N2O nitridation of fluorinated oxide (F-ox), grown at 900 °C with a 100 ppm NF3 additive, lies between 30 and 120 min at 950 °C. With careful control of fluorinated oxide growth parameters and N2O annealing, we have demonstrated an excellent way to fabricate dielectric thin films for future applications.

Thermal budget consideration in rapid isothermal processing

Rapid isothermal processing (RIP) based on incoherent radiation as the source of thermal and optical energy is emerging as a key low-thermal budget processing technique. Because of high heating and cooling rates, the RIP cycle generally refers to processing time and temperature. In this letter, we have shown that the properties of materials and devices fabricated by RIP depends on the heating and cooling rates. Optimized heating and cooling rates can minimize unwanted phenomena (e.g., higher thermal stress, warpage, etc.) leading to the improved performance of the devices fabricated by RIP. To demonstrate this significance of heating and cooling rates, we report the wafer dimensional analysis results for ramp rates of 15, 75, 100, 150, and 200 °C per second at a maximum steady-state temperature of 1050 °C. Plasma and low-pressure chemical vapor deposition silicon nitride films on 6-in. wafers were studied for warpage. The BF2 and As implanted wafers at a fixed dose of 8×1015/cm2 were studied for slow (15 °C per second) and fast (200 °C per second) ramp rates. We also present stress, secondary ion mass spectroscopy, and diode leakage current results for different RIP cycles of interest.

In-Situ Doped Multi-Layer Epitaxial Structures with Abrupt Doping Transitions by Ultra High Vacuum Rapid Thermal Chemical Vapor Deposition (UHV-RTCVD)

ABSTRACTIn this work, we have studied boron doped multi-layer epitaxial structures as active regions of deep submicron (< 0.25 gtm)metal oxide silicon field effect transistors (MOSFETs).The structures were formed by ultra high vacuum chemical vapor deposition (UHV-RTCVD) using Si2H6 and B2H6 as the source gases and H2 as the carrier gas at 750°C - 800°C and at a total pressure of 80 mTorr. With the high growth rates provided by Si2H6, thermal budgets were kept below the limit of boron diffusion in Si resulting in extremely abrupt doping transitions pushing the depth resolution limits of secondary ion mass spectroscopy. The structures consist of three epitaxial layers with thicknesses ranging from 100 A to 625 T. The top layer on which the gate oxide is formed is lightly doped (lxl016 cm-3) to minimize vertical electrical field and ionized impurity scattering for higher MOSFET channel mobility. The second layer is doped to lx1018 cm-3 for suppression of punchthrough short channel effects and finally the third layer is doped to lx 1017 cm-3 to decrease the parasitic source/drain junction capacitance that will result from the relatively high doping density of the intermediate layer. To minimize dopant diffusion in Si, low temperature (or low thermal budget) processes were employed for gate oxidation and polysilicon implant activation. A typical source/drain activation anneal was also included in sample preparation in order to simulate complete MOSFET fabrication assuming remaining steps could be carried out at lower temperatures with little contribution to dopant diffusion. Our results indicate that after all process steps a lightly doped region can still be obtained under the gate oxide with sufficient thickness to contain the MOSFET inversion layer. In these structures, the threshold voltage is determined by the doping density and thickness of the top two layers and can be easily tailored to the desired value by optimizing these parameters. With the range of parameters used in this study, our measurements show threshold voltages within the range desired for 0.1 µm MOSFETs.

Passivation of III-V Semiconductor Surfaces Using Light Assisted Integrated Processes

ABSTRACTPassivation of III-V semiconductor surfaces and especially the GaAs surface has been studied for over two decades without significant breakthrough. However, III-V device performances are still often limited by surface properties. In particular field effect behaviour in GaAs has been impossible to obtain due to the Fermi level pinning at the surface of this material. This paper presents an integrated sequence of low thermal budget processes to provide contamination control at the GaAs surface leading to very promising field effect on GaAs.In-situ surface cleaning using a Distributed Electron Cyclotron Resonance Microwave plasma (DECR MMP) has been integrated with a thin dielectric film deposition facility using light assisted CVD technics. Photoluminescence results carried out on GaAs surfaces have demonstrated that exposure to a hydrogen plasma induces lower recombination rates on these surfaces. Bulk diffusion of hydrogen during this process can be controlled and eliminated using an integrated Rapid Thermal Annealing (RTA). Finally, in-situ encapsulation by a dielectric allows one to stabilize the electronic properties of the surface for passivation applications. A silicon nitride film deposited by a direct UV photolysis deposition process has been developed for this study and is presented here.

Sputtered ferroelectric thin films for dynamic random access memory applications

Abstract A low thermal budget (with 550°C annealing) process with Ti-compensation for sputtered ferroelectric PZT thin films has been developed. PZT films with a composition near the morphotrophic phase boundary (Zr/Ti = 53/47) annealed at 550°C for 1 hr in a N2 ambient exhibits high charge storage density and low leakage current density, which are the important requirements of dielectric materials for ULSI DRAM cells. It was also found that Ti compensated films show good fatigue endurance in comparison with non-Ti compensated films.

Materials and device issues in the formation of sub-100-nm junctions

This paper compares the materials and device issues associated with two alternative techniques for the formation of ultrashallow junctions: 1) the use of preamorphization and low energy dopant implantation, combined with rapid, low-temperature annealing; and 2) the use of metal suicides as a diffusion source (SADS) where dopants are implanted into CoSi 2 and subsequently diffused into silicon. For conventionally-formed, ultrashallow junctions, preamorphization with either silicon or germanium does not result in shallower junctions. The enhanced diffusion associated with the preamorphization implant damage compensates for the reduction in channeling. Preamorphization does, however, give low sheet resistance junctions and high dopant activation after recrystallization at 550°C. Considerable dopant motion (∼ 50 nm) is observed in the tail region, near the junction, after 10 s of annealing at a relatively low temperature (800°C). The SADS process is seen to produce low leakage n + and p + diodes with less than 10 nm of dopant diffusion beyond the silicide/silicon interface, using a very low thermal budget process. By confining the implantation to within the suicide, no crystal defects are created in the underlying silicon. With the SADS process, the limitation on scaling the junction depth lies in producing thin, stable suicide films. Agglomeration of the silicide and pullback along feature edges restrict the maximum thermal cycle and the minimum allowable film thickness.

Improved ultrathin oxynitride formed by thermal nitridation and low pressure chemical vapor deposition process

In this letter, we will present the electrical and reliability characteristics of ultrathin oxynitrides (65–73 Å) formed by thermal nitridation of silicon substrate followed by deposition of silicon dioxide by low pressure chemical vapor deposition (LPCVD) technique. The dielectric integrity has been compared to those of the conventional thermal oxide and reoxidized nitrided oxides. It has been found that the new oxynitrides have lower electron trapping, higher charge-to-breakdown, and lower interface state generation under electrical stress even in comparison to reoxidized nitrided oxides with the same thermal budget. The improved characteristics are believed to be due to the combination of the nitrogen-rich layer at the Si/SiO2 interface, the higher quality of LPCVD oxides over thermally grown oxides, and the reduced hydrogen concentration in the dielectrics in comparison to conventional nitrided oxides. The results indicate that these new oxynitride films may be promising for ultra large scale integrated metal-oxide-semiconductor device applications, especially in cases where low thermal budget processes are desirable.

Variation in threshold voltage of n-MOS natural transistors

This work reports on the spread in threshold voltage and flat-band voltage of natural n-MOS enhancement mode transistors on the wafer and wafer-to-wafer processing by the low thermal budget process. It is shown that the threshold voltage (Vth) varies within ± 10mV to ±20mV around the average value of 0-44 V. The flat-band voltage (VFB) varies within ±15mV around the average value of 1 -05 V. The variation in VFB and Vth is also marginal from wafer-to-wafer.

Performance study of n-MOS natural transistor fabricated by low thermal budget process

Natural n-MOS transistor and MOS capacitor test structures have been fabricated by the low temperature process design for better control on device dimensions. Si-SiO 2 interface properties and performance of LPCVD gorwn polysilicon gate natural transistor has been studied through MOS C-V analysis and physical-electrical modeling. Transistor behavior at cryogenic temperatures has also been analysed through MOS C-V characteristics and one dimensional transport equations.