Abstract
Natural n-MOS transistor and MOS capacitor test structures have been fabricated by the low temperature process design for better control on device dimensions. Si-SiO 2 interface properties and performance of LPCVD gorwn polysilicon gate natural transistor has been studied through MOS C-V analysis and physical-electrical modeling. Transistor behavior at cryogenic temperatures has also been analysed through MOS C-V characteristics and one dimensional transport equations.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
