Low Temperature Post Annealing Research Articles

Approach to Low Contact Resistance Formation on Buried Interface in Oxide Thin-Film Transistors: Utilization of Palladium-Mediated Hydrogen Pathway.

Amorphous oxide semiconductors (AOSs) with low off-currents and processing temperatures offer promising alternative materials for next-generation high-density memory devices. The complex vertical stacking process of memory devices significantly increases the probability of encountering internal contact issues. Conventional surface treatment methods developed for planar devices necessitate efficient approaches to eliminate contact issues at deep internal interfaces in the nanoscale complex structures of AOS devices. In this work, we report the pioneering use of palladium thin film as a high-efficiency active hydrogen transfer pathway from the outside to the internal contact interface via low-temperature postannealing in the H2 atmosphere, and the formation of highly conductive metallic interlayer effectively solves the contact issues at the deeply buried interfaces in devices. The application of this method reduced the contact resistance of Pd electrodes/amorphous indium-gallium-zinc oxide (a-IGZO) thin-film by 2 orders of magnitude, and thereby the mobility of thin-film transistor was increased from 3.2 cm2 V-1 s-1 to nearly 20 cm2 V-1 s-1, preserving an excellent bias stress stability. This technology has wide applicability for the solution of contact resistance issues in oxide semiconductor devices with complex architectures.

Tuning the structural, magnetic, and transport properties of Mn3Ga alloys

Mn3Ga alloys with different crystal modifications, including a disordered L12-type cubic structure, a D022-tetragonal structure, and a D019-hexagonal structure showing two isomorphic heteromagnetic phases, ε-phase and η-phase, were investigated systematically. We found that the disordered cubic phase and the hexagonal ε-phase can be synthesized with Mn compositions ranging from 70 to 75 at. % by rapid melt-spinning. Moreover, the disordered cubic phase could transform to the tetragonal phase after being subjected to low-temperature postannealing. Most importantly, we found that proper postannealing conditions can enable these different crystal modification phases to transform to the hexagonal η-phase. As a result, the two isomorphic heteromagnetic hexagonal phases are clearly distinguished, and their interesting magnetic and transport properties are discussed.

Posttreatment Effects on the Crystal Structure and Superconductivity of Ca-Free Double-Layered Cuprate Sr2SrCu2O4+yF2–y

We report the effects of low-temperature postannealing on the structural and superconducting properties of the recently discovered Ca-free double-layered cuprate, Sr$_2$SrCu$_2$O$_{4+y}$F$_{2-y}$. Although the as-synthesized sample prepared under high pressure has a tetragonal structure with a rock-salt-type blocking layer (the so-called $T$-phase), we found that the symmetry of the structure lowered to that of an orthorhombic system when annealed with CuF$_2$. The structural refinements reveal that such a topochemical reaction leads not only to the removal of excess O$^{2-}$ from the apical site but also to the intercalation of extra F$^-$ into the interstitial site. The orthorhombic phase exhibits bulk superconductivity at a critical temperature of 107 K, which is significantly higher than that of the $T$-phase ($\sim$50 K). Meanwhile, the $T$-phase turns into another structure possessing a fluorite-type blocking layer without apical fluorine (known as the $T^\prime$-phase) by annealing without CuF$_2$. Density functional theory calculations show that the $T^\prime$-phase is more stable than the $T$-phase. This is the first report on the formation of a $T^\prime$-type double-layered cuprate. Furthermore, the structural stability of the three phases of Sr$_2$SrCu$_2$O$_{4+y}$F$_{2-y}$ is discussed in terms of lattice matching between the blocking and conducting layers.

Stress Writing Textured Graphite Conducting Wires/Patterns in Insulating Amorphous Carbon Matrix as Interconnects

This study reports a mechanical stress-based technique that involves scratching or imprinting to write textured graphite conducting wires/patterns in an insulating amorphous carbon matrix for potential use as interconnects in future carbonaceous circuits. With low-energy post-annealing below the temperature that is required for the thermal graphitization of amorphous carbon, the amorphous carbon phase only in the mechanically stressed regions transforms into a well aligned crystalline graphite structure with a low electrical resistivity of 420 μΩ-cm, while the surrounding amorphous carbon matrix remains insulating. Micro-Raman spectra with obvious graphitic peaks and high-resolution transmission electron microscopic observations of clear graphitic lattice verified the localized phase transformation of amorphous carbon into textured graphite exactly in the stressed regions. The stress-induced reconstruction of carbon bonds to generate oriented graphitic nuclei is believed to assist in the pseudo-self-formation of textured graphite during low-temperature post annealing.

Different Bandgaps in Cu$_2$ ZnSnSe$_4$: A High Temperature Coevaporation Study

We present a high-temperature Cu $_2$ ZnSnSe $_4$ coevaporation study, where solar cells with a power conversion efficiency of 7.1% have been achieved. The process is monitored with laser light scattering in order to follow the incorporation of the Sn into the film. We observe the segregation of ZnSe at the Mo/CZTSe interface. Optical analysis has been carried out with photoluminescence and spectrophotometry. We observe strong band tailing and a bandgap, which is significantly lower than in other reported efficient CZTSe absorbers. The photoluminescence at room temperature is lower than the bandgap due to the existence of a large quantity of tail states. Finally, we present effects of low-temperature postannealing of the absorbers on ordering of the Cu/Zn atoms in CZTSe and solar cell parameters. We observe strong changes in all solar cell parameters upon annealing. The efficiency of the annealed devices is significantly reduced, although ordering is improved compared with ones made from nonannealed absorbers.

Self-Passivation by Fluorine Plasma Treatment and Low-Temperature Annealing in SiGe Nanowires for Biochemical Sensors

Nanowires are widely used as highly sensitive sensors for electrical detection of biological and chemical species. Modifying the band structure of strained-Si metal-oxide-semiconductor field-effect transistors by applying the in-plane tensile strain reportedly improves electron and hole mobility. The oxidation-induced Ge condensation increases the Ge fraction in a SiGe-on-insulator (SGOI) and substantially increases hole mobility. However, oxidation increases the number of surface states, resulting in hole mobility degradation. In this work, 3-aminopropyltrimethoxysilane (APTMS) was used as a biochemical reagent. The hydroxyl molecule on the oxide surface was replaced by the methoxy groups of the APTMS molecule. We proposed a surface plasma treatment to improve the electrical properties of SiGe nanowires. Fluorine plasma treatment can result in enhanced rates of thermal oxidation and speed up the formation of a self-passivation oxide layer. Like a capping oxide layer, the self-passivation oxide layer reduces the rate of follow-up oxidation. Preoxidation treatment also improved the sensitivity of SiGe nanowires because the Si-F binding was held at a more stable interface state compared to bare nanowire on the SiGe surface. Additionally, the sensitivity can be further improved by either the N2 plasma posttreatment or the low-temperature postannealing due to the suppression of outdiffusion of Ge and F atoms from the SiGe nanowire surface.

Annihilation of photo induced minority carrier caused by ion implantation and rapid thermal annealing

We report decreases in the minority carrier effective lifetime τeff of 700-µm-thick silicon substrates coated with 43-nm-thick thermally grown SiO2 layers by Ge ion implantation with a dose of cm−2 at 150 keV and rapid thermal annealing (RTA) at 1100 °C for 50 s. Ge ion implantation decreased the crystalline volume ratio in the top 157 nm region because of lattice damage. It also markedly decreased τeff to and s when 635 and 980 nm lights were continuously illuminated to the implanted surface, respectively. Small τeff values resulted from serious damage with a high surface recombination velocity S of cm/s and a short bulk lifetime of s in the 200 µm deep surface region. Although RTA successfully recrystallized the Ge-implanted surface region, it further decreased τeff to and s in the cases of 635 and 980 nm light illuminations to the top surfaces, respectively. RTA caused a high density of recombination sites with a high S value of cm/s on the top and rear surfaces. There was a high density of interface traps of eV−1 cm−2. Pa H2O vapor heat treatment at 260 °C for 3 h markedly increased τeff to and s in the cases of 635 and 980 nm light illuminations. The interface trap density was decreased to eV−1 cm−2. Low temperature post annealing is effective in curing the recombination defect states induced by RTA.

Optimization of the Fabrication Process for ZnO Thin-Film Transistors with HfO2 Gate Dielectrics

In this work, we address the analysis of ZnO thin films and electrical characteristics of ZnO thin film transistors (TFTs) with HfO2 high-k gate dielectrics after low-temperature postannealing. The SIMS analysis shows that the diffusion of Zn atoms into the HfO2 gate dielectrics will occur after 300 °C annealing and the related electrical characteristics indicate that 200 °C annealing will be the suitable annealing condition for ZnO/HfO2/ITO-based TFTs. The ZnO TFTs after 200 °C annealing exhibited transistor behavior over the range of 0–7 V; the field effect mobility, subthreshold slope, and on/off ratio were measured to be 1.3 cm2 V-1 s-1, 0.5 V/decade, and ∼106, respectively.

Low Temperature Post-Annealing of ZnO Thin-Film Transistors with High-k Gate Dielectrics

This work addresses the thin film analysis of ZnO and electrical characteristics of ZnO TFTs with HfO2 high-k gate dielectrics after low temperature post-annealing. The SIMS analysis shows that the diffusion of Zn atoms into the HfO2 will occur after 300 oC annealing and the related electrical characteristics indicates that the 200 oC annealing will be the optimized annealing condition for the ZnO/HfO2/ITO based TFTs. The ZnO TFTs after optimized annealing condition exhibited transistor behavior over the range 0-7 V; the field effect mobility, subthreshold slope and on/off ratio were measured to be 1.3 cm2V-1s-1, 0.5 V/decade and ~106, respectively.

Low-Temperature Annealing of n-Type β-FeSi2/p-Type Si Heterojunctions

β-FeSi2 thin films epitaxially grown on Si(111) were annealed in vacuum at different annealing temperatures. The effects of low-temperature postannealing on the photovoltaic properties of β-FeSi2/Si heterojunctions were investigated. The heterojunctions annealed at 300 °C exhibited an apparent improvement in photovoltaic performance as compared with as-grown heterojunctions. This improvement may be due to Fe atoms, that diffused into the Si substrate during β-FeSi2 film deposition, were gettered by the postannealing process.

Effects of low-temperature postannealing on a n+-p shallow junction fabricated by plasma doping

A low-temperature activation annealing process following plasma doping (PLAD) was investigated. A dramatic reduction of sheet resistance Rs occurred in the postactivation annealing temperature range of 400°C–480°C after PLAD. The Rs of 30Ω∕sq. and the junction depth Xj of 30nm was obtained without the additional diffusion of a dopant from the postactivation annealing in the fabricated junction. The electrical characteristics of a n+-p junction diode fabricated by PLAD were also improved after low-temperature postannealing.

Increasing coercivity of CoCrTaPt/Cr thin film media by interdiffusion of Mn and Cu overlayers by low temperature annealing

Mn and Cu overlayers were studied with CoCrTaPt/Cr films on glass substrates. Low temperature postannealing reveals an increase in the in-plane coercivity of 700 Oe for Mn and 400 Oe for Cu. X-ray diffraction patterns indicate that the change in magnetic properties is unlikely due to the improvement of crystalline structure. It is suggested that the interdiffusion between magnetic layer and overlayer plays a key role in the coercivity increase. ΔM curves show reduced exchange coupling between grains. It is believed that during low temperature annealing, the diffusion of the overlayer atoms most likely occurs at the grain boundaries, which results in better segregation between grains that may lead to higher coercivity and lower media noise.

Effect of low temperature postannealing on the hole density of C δ-doped GaAs and Al0.3Ga0.7As

In C δ-doped GaAs and Al0.3Ga0.7As grown by metalorganic vapor phase epitaxy using trimethylaluminium as a doping precursor, 20%–50% of the C acceptors are not electrically active due to hydrogen passivation. These hydrogen passivated C acceptors can be activated by low temperature postannealing in the N2 ambient. The amount of activated C acceptors depends on the postannealing temperature and postannealing time. After ∼10 min postannealing at 530 °C, most of hydrogen passivated C acceptors are activated, leading to a constant hole density with a further increase in postannealing time. At a given postannealing time of 15 min, an increased temperature always activates more hydrogen passivated C acceptors. There is no measurable change in the hole density after 15 min postannealing at temperatures below 450 °C. The activated C acceptors can be re-passivated by heating the postannealed C δ-doped (Al,Ga)As to 480 °C in the AsH3/H2 ambient but not in the H2 ambient. The as-grown C δ-doped GaAs with much less hydrogen passivation can be grown using the H2 cooling ambient.

Type conversion of (Hg,Cd)Te induced by the redistribution of residual acceptor impurities

Bulk (Hg,Cd)Te grown by the quench-anneal process has been found to contain residual acceptor impurities which are normally depleted from the n-type surface by an internal gettering mechanism during low temperature postannealing in saturated Hg vapor. When the n-type slices are postannealed for much longer periods, the Te saturated core is annihilated, and the gettered residual acceptor impurities can redistribute into the surface region. If upon homogenization the residual acceptor concentration exceeds the residual donor concentration, the material will convert to p type. A new method for applying neutron activation analysis (NAA) to (Hg,Cd)Te has been used to identify this acceptor impurity as Cu at levels below 1 ppm. An extension of the NAA technique has employed quartz encapsulated silicon samples to demonstrate Cu may come from either the quartz or annealing environment.