Low-temperature Polycrystalline Silicon Research Articles

Vertical ITO/SiOX/a-Si:H Photodiode-Gated Low-Temperature Polycrystalline Silicon Thin-Film Transistor Intended for In-Display Fingerprint Imaging Applications

To embed an active pixel optical sensor in a display pixel for fingerprint imaging, an area-efficient and vertical ITO/SiOX/a-Si:H photodiode-gated low-temperature polycrystalline silicon dual-gate thin-film transistor with controllable photosensitivity is proposed and experimentally demonstrated. The device can be operated as a driving switch to the display pixel, and the driving current is insensitive to normal ambient light; the device can also be operated as an optical sensor, which provides 8 bits of effective data and reasonable detectable intensity range. The compact structure and dual-mode operation make it a promising solution to in-display, large-area fingerprint identification for smartphones.

Photosensing circuit using thin-film transistors for retinal prosthesis

A photosensing circuit using thin-film transistors (TFTs) for a retinal prosthesis has been developed. First, the TFTs that are low-temperature polycrystalline silicon (poly-Si) TFTs are fabricated on a transparent substrate, which enables us to build an epiretinal implantation system without using any extracorporeal cameras. Then, the photosensing circuit is fabricated by connecting a p/i/n-type phototransistor and a ring oscillator, which provides stimulating current pulses with an oscillation frequency dependent on light illuminance. In particular, the device structure of the p/i/n-type phototransistor is designed well on the basis of device physics, and the configuration of the photosensing circuit on the basis of device characteristics. Subsequently, a wireless power transfer system is architected by magnetic resonance coupling. Finally, a retinal prosthesis is produced by assembling the photosensing circuit and wireless power transfer system, and the stimulating performance is confirmed in an in vitro experiment, which suggests a future possibility of this retinal prosthesis.

Bottom-Metal Induced Leakage Current of LTPS Diode for ESD Protection

Leakage current behavior was investigated for diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in display product with high luminance backlight system. In this study, the bottom metal layer was adopted to suppress leakage current caused by light coming from backlight system. Different off-current behavior as each other electrical connection of metal layer was observed, source-contacted or floating bottom metal showed the high leakage current by increasing current flow through back-channel at off states while gate-contacted bottom metal have comparable low leakage current with non-bottom metal layer. This leakage current characteristic was verified by technology computer-aided design (TCAD) simulation. Objectives and Background A low temperature polycrystalline silicon (LTPS) have been widely used for in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode displays (AMOLEDs) as thin film transistor (TFT) backplane and system on panel (SOP), combined with controller, memory, and driver circuits, due to excellent electrical characteristics. The LTPS TFT based displays can achieve high brightness, high aperture ratio, high resolution, and low power consumption due to excellent electrical characteristics. On the other hand, in display product with high luminance backlight system, such as auto and mobile products, the LTPS TFTs require a bottom metal layer to reduce leakage current caused by light coming from backlight unit (BLU). This bottom metal layer in contacted with gate or source electrodes is applied under the poly-Si layer. However, this bottom metal layer may also affect seriously the leakage current of diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in SOP. In this study, the leakage current of LTPS diode for ESD protection was investigated with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. We measured the electrical characteristics with variation of electrical connection of bottom metal layer. Also, the technology computer-aided design (TCAD) simulation was performed to analyze the physical mechanism. From analysis results, optimized bottom metal design of LTPS diode was proposed for ESD production. Experiment Figure 1 shows the top-gate coplanar n-channel LTPS TFT structure with bottom metal layer under poly-Si. Gate and Drain electrodes were connected to common electrode in LTPS TFTs structure for LTPS diode. This LTPS diode was fabricated at low temperature of less than 450°C on glass substrate. The standard commercial NMOS processes, including the ion implantation, the excimer laser annealing (ELA), and the rapid thermal annealing (RTA), were employed in this experiment. To observe the electrical characteristics of LTPS diode, I-V characteristics were measured by using an Agilent B1500A semiconductor analyzer at room temperature. Results and Discussion Figure 2 shows I-V characteristics of LTPS diodes with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. The leakage current with source-contacted and floating bottom metal increased considerably compared with non-bottom metal. Especially, the leakage current with source-contacted bottom metal increased more than with floating bottom metal. On the other hand, the leakage current with gate-contacted bottom metal was low enough to be comparable with non-bottom metal. To analyze this phenomenon, we observed the electron concentration distribution within poly-Si at VGS= 0V, 10V, and -10V region using technology computer-aided design (TCAD) simulation as shown figure 3. For source-contacted bottom metal and floating bottom metal, at VGS= -10V, the electron was accumulated in the back-channel of poly-Si since the positive voltage is applied to back-channel by voltage difference between drain and bottom metal even though drain (=gate) electrode is applied to negative voltage. Therefore, at VGS= -10V, the leakage current flows through the back-channel in LTPS diodes with source-contacted bottom metal and floating bottom metal. But, for LTPS diode with gate-contacted bottom metal, when drain electrode was applied to negative voltage, there is no different voltage bottom metal and gate electrode because these electrodes were linked in common. Therefore, LTPS diode with gate-contacted bottom metal has low leakage current as comparable with non-bottom metal. Conclusion In summary, the leakage current of LTPS diode was strongly dependent on electrical connection of bottom metal layer. The electrical connection of bottom metal affects back-channel region within poly-Si due to the difference between bottom metal and drain electrodes at off region. Especially, LTPS diode with source-contacted bottom metal and floating bottom metal increased considerably the leakage current, while, gate-contacted bottom metal decreased leakage current. Therefore, bottom metal layer should be connected by gate electrode in LTPS diode for ESD protection. Figure 1

Integration Challenges of Flash Lamp Annealed LTPS for High Performance CMOS TFTs

The development of low-temperature polycrystalline silicon (LTPS) based on excimer laser annealing (ELA) has realized CMOS TFTs with notable electrical performance. The flat-panel display industry is searching for alternative LTPS strategies which are cost-effective and easily scalable to large glass panel production, which has led to recent interest in the application of flash-lamp annealing (FLA) for the LTPS crystallization process. The FLA-LTPS process exposes large areas of amorphous silicon with high irradiance from xenon flashlamps for pulse durations that are in microsecond timescale. Amorphous silicon absorbs a sufficient portion of the xenon emission spectrum to melt and crystallize into polysilicon while staying within the thermal constraints of the underlying glass substrate. Multi-lamp exposure systems with high repetition pulse rates would potentially offer significant advantages in manufacturing throughput and cost. The application of FLA-LTPS for CMOS TFTs has been recently reported, with best-case performance comparable to ELA-LTPS. Investigations to improve upon this technology are in progress to address integration challenges to reduce variation in device operation and enable device scaling. The focus areas of this work are material uniformity, source/drain dopant activation, and defect passivation; all of which are fundamental issues facing FLA-LTPS TFTs. The importance of patterning the amorphous silicon film into separate super-mesa elements prior to FLA crystallization was previously established. The FLA system for this work was a NovaCentrix PulseForge 3300 system, used to crystallize polygons of a-Si with a 100 nm SiO2 capping layer. The FLA response of densely packed mesa arrays exhibits a proximity effect which impedes the melting of interior mesas, whereas exterior mesas demonstrate a crystallization response consistent with isolated mesas. This comparison is highlighted in Fig. 1 by the pronounced gradient in crystallization morphology. These observations have led to a theory of competing rates between solid-phase and liquid-phase crystallization, hypothesized due to the large difference between the melting points of amorphous and crystalline silicon. The challenge of dopant activation is exacerbated by the need to limit lateral diffusion. Dopants within silicon that has entered a liquid phase will experience dramatically enhanced diffusion, even within the ultra-short pulse duration of the FLA process. The result is a compromised intrinsic channel which limits device scaling. Thus, dopants must be introduced into post-FLA LTPS and activated at glass-compatible temperatures, which is also a requirement for self-aligned devices. Solid-phase dopant activation in FLA-LTPS films has been investigated using furnace annealing and multiple shot FLA exposures at lower intensity. Pre-amorphizing the source/drain regions with electrically inactive species has also been explored. Hydrogen passivation treatments using both plasma and sintering processes have been investigated in efforts to reduce the influence of defect states. Pre-amorphization and passivation processes have yielded promising device characteristics with low series resistance, low leakage current, and high carrier mobility, as shown in Fig. 2. Figure 1

Bottom-Metal Induced Leakage Current of LTPS Diode for ESD Protection

Leakage current behavior was investigated for diode-connected low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) with the coplanar structure for electrostatic discharge (ESD) protection in display product with high luminance backlight system. In this study, the bottom metal (BM) layer was adopted to block lights coming from backlight system. We observed different leakage current behaviors as each other electrical connection of BM layer, such as floating BM (FBM), source-contacted BM (SBM), and gate-contacted BM (GBM). In particular, when negative voltage is applied, LTPS diodes with SBM and FBM show the high leakage current by increasing current flow through back-channel. On the other hand, GBM has comparable low leakage current with non-BM. These leakage current characteristics were verified by technology computer-aided design (TCAD) simulation.

Vertically Integrated Optical Sensor With Photoconductive Gain > 10 and Fill Factor > 70%

A hybrid active pixel optical sensor for high-resolution and high-sensitivity imaging is proposed and experimentally demonstrated. The sensor vertically integrates an amorphous silicon p-i-n photodiode and a low-temperature polycrystalline silicon readout thin-film transistor (TFT). The vertical integration results in a high fill factor (>70%) and an enlarged photosensing area in the pixel. In the photodiode-gated TFT structure of the sensor, the output current is amplified by operating the TFT in the sub-threshold regime. A weak wavelength-dependent photoconductive gain >10 is obtained at visible wavelengths, enabling large area low-level light detection.

Performance of four-terminal low-temperature polycrystalline-silicon thin-film transistors and their application in CMOS inverters on glass substrates

High-performance and low-power-operation CMOS circuits comprising low-temperature (LT) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) are indispensable for integrated circuits on glass substrate. The fabrication of high-quality poly-Si films with large grains can enhance the on-current of TFTs on glass substrates owing to low carrier scattering. In this study, we used continuous-wave laser lateral crystallization (CLC) to fabricate high-quality thin poly-Si films on a glass substrate. To achieve low-power operation, precise threshold voltage (Vth) control is most important, and four-terminal (4T) TFT is one attractive approach to achieve it. We fabricated a CMOS inverter comprising 4T CLC LT poly-Si TFTs on a glass substrate and confirmed nearly identical controllability of Vth, subthreshold swing, and mobility of n- and p-channel TFTs in CMOS inverter as compared with TFTs fabricated on different glass substrates with their own processes. By using the high controllability of 4T CLC LT poly-Si TFTs, we successfully operated the CMOS inverter with Vdd = 1.0 V.

Modelling localized charge-injection region of the p-channel low-temperature polycrystalline silicon thin-film transistor

The low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) is the optimal device for the backplane of the organic light-emitting diode display. At the end the p-channel LTPS TFT fabrication, a charge-injection stress with a strong negative drain bias and a positive gate bias are applied to reduce the off-current by injecting electrons into the gate insulator near the drain. In this study, the charge density and the length of the charge-injection region in the gate insulator were estimated by comparing the measured TFT characteristics with the simulation models with various charge-injection lengths and charge densities. It was found that the effective length of the charge-injection region was 0.96 µm and the charge density was −3 × 1012/cm2 for the 2-µm-channel-length device when VGS was +20 V and VDS was −10 V under the charge-injection stress condition. It was also found, based on the analysis of the electric field distribution under the bias stress condition, that the charge density and the length of the charge-injection region were invariant against the channel length variation. Therefore, the measured TFT characteristics also accorded closely with the simulation models for different channel lengths, such as 4 and 10 µm, when the same characteristic values of the charge-injection region were employed.

Anomalous Kink Effect Induced by Bottom-Shield-Metal in LTPS TFTs on Plastic Substrates

The anomalous kink effect was investigated in n-type low-temperature polycrystalline silicon thin-film transistors with the source-contacted bottom-shield-metal (SBSM) layer on a polyimide substrate. Using experiments and technology computer-aided design simulation, it was found that the SBSM layer plays a critical role in the anomalous kink effect. The SBSM layer modulated the carrier concentration within the lightly doped drain (LDD) region according to the applied drain voltage ( $\text{V} _{\text{DS}}$ ). In addition, this carrier modulation caused changes in the lateral electric field at simultaneously the channel/LDD junction and the LDD/n+ junction. Thus, multiple kink effects, different from the conventional kink effect, occurred in two different $\text{V} _{\text{DS}}$ regions with different slopes depending on the LDD length ( $\text{L}_{\text{LDD}}$ ) and the overlap length ( $\text{L}_{\text{BSM}}$ ) between the LDD region and the SBSM layer in the drain region. We propose a novel asymmetric design to suppress the SBSM-induced anomalous kink effect in all $\text{V}_{\text{DS}}$ regimes. This design has the following requirements with respect to $\text{L}_{\text {LDD}}$ and $\text{L}_{\text {BSM}}$ at the drain region: $\text{L}_{\text {BSM}}$ greater than $1.0~\mu \text{m}$ , $\text{L}_{\text {LDD}} - \text{L}_{\text {BSM}}$ (LLDD) greater than $1.0~\mu \text{m}$ , and $\text{L}_{\text {BSM}}$ equal to half of $\text{L}_{\text {LDD}}$ .

Analysis of defects in low-temperature polycrystalline silicon thin films related to surface-enhanced Raman scattering

The analysis of Raman scattering (RS) spectroscopy is presented for low-temperature polycrystalline silicon (poly-Si) thin films on glass substrates fabricated by excimer laser crystallization. In this material, RS is enhanced by specific protrusions at the grain boundary (GB). As a result, the Si lattice mode predominantly reflects the characteristics of GB and its neighborhood. A combination of low-damage hydrogenation and RS analysis enables the detection of lattice defects as Si–hydrogen (H) local vibration modes (LVMs). The characteristics of LVMs peculiar to this material are examined by chemical etching and postannealing. One of the dominant LVMs centered at ∼2000 cm−1 is assigned to H-terminated dangling bonds in the amorphous structures at GB, which is also enhanced by protrusions. The other dominant band centered at ∼2100 cm−1 is attributed to the strained Si–Si lattice near the Si/underlayer interface in grains that is broken and stabilized by extrinsic H atoms.

Effect of selectively passivated layer on foldable low temperature polycrystalline silicon thin film transistor characteristics under dynamic mechanical stress

For the next generation display, foldable display is one of the attractive candidates. However, the degradation effects due to the mechanical stress on the device are unavoidable. A strain due to the mechanical stress generates cracks on the thin film transistors (TFTs). In this case, if the methodology guiding cracks is applied in the fabrication process, the device reliability can be enhanced. In this paper, a crack guided layer followed by the device fabrication process is deposited on p-type low temperature polycrystalline silicon (LTPS) TFT. Statistical analysis is also used to analyze the crack guided layer effects. To apply a strain on the foldable LTPS TFTS, 5000cycles of dynamic mechanical stress with tensile and perpendicular directions were applied with 2-mm bending radius. Based on the results, TFT reliability can be enhanced by controlled the crack position using the crack-guided passivation layer.

Investigation of the drain-induced barrier lowering of low-temperature polycrystalline silicon TFTs depending on the grain configuration and channel length

ABSTRACTThe transistor size needs to be reduced as the pixel density of the organic light-emitting diode (OLED) display increases for mobile application. Drain-induced barrier lowering (DIBL), however, hinders the further channel length reduction of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs), which leads to severe mura of the OLED display for the low-gray level. The two-dimensional device simulation analysis showed that the potential energy barrier for the holes in the p-channel TFT decreases as the drain voltage intensifies from −1 to −10 V. The barrier lowering becomes severe as the channel length is reduced from 5 to 2 µm, but it does not have any noticeable dependency on the grain size variation from 0.3 to 0.5 µm. It was also found that the degree of DIBL varies considerably depending on the position of the grain boundary even for the same grain size, as the channel length is reduced. It was determined from the analysis that was conducted in this study that the deviation of the subthreshold current for the variation of the grain size and the grain boundary location increases 64 times as the channel length is reduced from 5 to 2 µm.

The effect of a source-contacted light shield on the electrical characteristics of an LTPS TFT

The electrical characteristics of a low-temperature polycrystalline silicon thin-film transistor (TFT) with a source-contacted light shield (SCLS) are observed and analyzed. Compared with that of a conventional TFT without a light shield (LS), the on-current of the TFT with an SCLS is lower because the SCLS blocks the fringing electric field from the drain to the active layer. Furthermore, the gate-to-source capacitance (Cgs) of the TFT with an SCLS in the off and saturation regions is higher than that of a conventional TFT, which is due to the gate-to-LS capacitance (Cg-LS). The electrical characteristics of the TFT with an SCLS are thoroughly investigated by two-dimensional device simulations, and a semi-empirical Cg-LS model for SPICE simulation is proposed and verified.

Theoretical investigation of the noise performance of active pixel imaging arrays based on polycrystalline silicon thin film transistors.

Active matrix flat-panel imagers, which typically incorporate a pixelated array with one a-Si:H thin-film transistor (TFT) per pixel, have become ubiquitous by virtue of many advantages, including large monolithic construction, radiation tolerance, and high DQE. However, at low exposures such as those encountered in fluoroscopy, digital breast tomosynthesis and breast computed tomography, DQE is degraded due to the modest average signal generated per interacting x-ray relative to electronic additive noise levels of ~1000e, or greater. A promising strategy for overcoming this limitation is to introduce an amplifier into each pixel, referred to as the active pixel (AP) concept. Such circuits provide in-pixel amplification prior to readout as well as facilitate correlated multiple sampling, enhancing signal-to-noise and restoring DQE at low exposures. In this study, a methodology for theoretically investigating the signal and noise performance of imaging array designs is introduced and applied to the case of AP circuits based on low-temperature polycrystalline silicon (poly-Si), a semiconductor suited to manufacture of large area, radiation tolerant arrays. Computer simulations employing an analog circuit simulator and performed in the temporal domain were used to investigate signal characteristics and major sources of electronic additive noise for various pixel amplifier designs. The noise sources include photodiode shot noise and resistor thermal noise, as well as TFT thermal and flicker noise. TFT signal behavior and flicker noise were parameterized from fits to measurements performed on individual poly-Si test TFTs. The performance of three single-stage and three two-stage pixel amplifier designs were investigated under conditions relevant to fluoroscopy. The study assumes a 20×20cm2 , 150μm pitch array operated at 30fps and coupled to a CsI:Tl x-ray converter. Noise simulations were performed as a function of operating conditions, including sampling mode, of the designs. The total electronic additive noise included noise contributions from each circuit component. The total noise results were found to exhibit a strong dependence on circuit design and operating conditions, with TFT flicker noise generally found to be the dominant noise contributor. For the single-stage designs, significantly increasing the size of the source-follower TFT substantially reduced flicker noise - with the lowest total noise found to be ~574e [rms]. For the two-stage designs, in addition to tuning TFT sizes and introducing a low-pass filter, replacing a p-type TFT with a resistor (under the assumption in the study that resistors make no flicker noise contribution) resulted in significant noise reduction - with the lowest total noise found to be ~336e [rms]. A methodology based on circuit simulations which facilitates comprehensive explorations of signal and noise characteristics has been developed and applied to the case of poly-Si AP arrays. The encouraging results suggest that the electronic additive noise of such devices can be substantially reduced through judicious circuit design, signal amplification, and multiple sampling. This methodology could be extended to explore the noise performance of arrays employing other pixel circuitry such as that for photon counting as well as other semiconductor materials such as a-Si:H and a-IGZO.

Dimension dependent immunity of X-ray irradiation on low-temperature polycrystalline-silicon TFTs

Typically, each element in a large-area flat-panel X-ray image sensor consists of a photodetector and amorphous silicon (a-Si) thin-film transistor (TFT) switches. In order to reduce noise, increase sensor dynamic range, and increase carrying capacity, the low-temperature polycrystalline-silicon (LTPS) TFTs have been proposed as a candidate to replace the a-Si TFTs. However, there are concerns regarding the impact of X-ray radiation in LTPS-TFTs, and several studies have been conducted to inquire into the same. In this paper, we show that LTPS TFTs with small channel length (<2 µm) are almost immune to X-ray radiation.

P‐128: Stress Absorbing LTPS‐TFT for Highly Flexible AMOLED

Low temperature polycrystalline silicon (LTPS) TFT with stress‐absorbing (SA) structure for reducing the strain on a flexible polyimide (PI) substrate was successfully developed and demonstrated. It shows a good flexible TFT performance even under the bending radius of 2 mm for 100,000 bending times.

Effects of mechanical stresses on the reliability of low-temperature polycrystalline silicon thin film transistors for foldable displays

This paper investigates the mechanical reliability of low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) for foldable display. Both compressive and tensile directions of mechanical stresses were applied for different types of mechanical stresses, such as dynamic and static mechanical stresses. The electrical characteristics of tested n-channel TFTs under mechanical stress conditions were analyzed based on several key parameters, including the threshold voltage (Vth), field effect mobility (μFE), maximum drain current (ID.MAX) and subthreshold swing (Ssub). For both cases of dynamic and static mechanical stresses, increase of Vth and decrease of μFE and ID.MAX were observed in the compressive direction. This trend was inversed when tensile stress was applied. The degradation of electrical characteristics originates from the change of lattice constant after mechanical stress. However, Ssub increases under dynamic tensile stress while it remains unchanged within 5% under static tensile stress. Transient analysis while bent condition was conducted to investigate the change of parameters in time.

Power saving through state retention in IGZO-TFT AMOLED displays for wearable applications

We present a qHD (960 × 540 with three sub-pixels) top-emitting active-matrix organic light-emitting diode display with a 340-ppi resolution using a self-aligned IGZO thin-film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven-layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low-temperature polycrystalline silicon. By using an IGZO thin-film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.

Effect of nickel silicide gettering on metal-induced crystallized polycrystalline-silicon thin-film transistors

Low-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) fabricated via metal-induced crystallization (MIC) are attractive candidates for use in active-matrix flat-panel displays. However, these exhibit a large leakage current due to the nickel silicide being trapped at the grain boundaries of the poly-Si. We reduced the leakage current of the MIC poly-Si TFTs by developing a gettering method to remove the Ni impurities using a Si getter layer and natively-formed SiO2 as the etch stop interlayer. The Ni trap state density (Nt) in the MIC poly-Si film decreased after the Ni silicide gettering, and as a result, the leakage current of the MIC poly-Si TFTs decreased. Furthermore, the leakage current of MIC poly-Si TFTs gradually decreased with additional gettering. To explain the gettering effect on MIC poly-Si TFTs, we suggest an appropriate model.

Electronically Pure Single Chirality Semiconducting Single-Walled Carbon Nanotube for Large Scale Electronic Devices

Abstract Carbon nanotube thin film transistors (TFTs) with characteristics resembling those of TFTs constructed on amorphous silicon, low-temperature polycrystalline silicon and metal oxides were fabricated on (6,5) single chirality single-walled carbon nanotube (SWCNT) thin film deposited from electronically pure semiconducting (6,5) single chirality single-walled carbon nanotube (SWCNT) ink. This ink was extracted in industrial scale from raw SWCNTs produced using high pressure carbon monoxide conversion, and deposited on pretreated substrates to form uniform and consistent (6,5) HiPCO SWCNT thin film using solution process. The (6,5) HiPCO SWCNT thin films were characterized as pure semiconductor without metallic impurities showing classic nonlinear current-bias curves in Schottky-type diodes. Both N-type and P-type (6,5) HiPCO SWCNT TFTs were fabricated with femto Ampere off-current and ION/IOFF ratio of 108 by depositing SiNx and HfO2 dielectrics on the top of (6,5) HiPCO SWCNT thin films, respectively. The (6,5) HiPCO SWCNT inverter with voltage gain of 52 was also demonstrated by wire-bonding one P-type HiPCO SWCNT TFT to one N-type HiPCO SWCNT TFT.