Effect of selectively passivated layer on foldable low temperature polycrystalline silicon thin film transistor characteristics under dynamic mechanical stress

Abstract

For the next generation display, foldable display is one of the attractive candidates. However, the degradation effects due to the mechanical stress on the device are unavoidable. A strain due to the mechanical stress generates cracks on the thin film transistors (TFTs). In this case, if the methodology guiding cracks is applied in the fabrication process, the device reliability can be enhanced. In this paper, a crack guided layer followed by the device fabrication process is deposited on p-type low temperature polycrystalline silicon (LTPS) TFT. Statistical analysis is also used to analyze the crack guided layer effects. To apply a strain on the foldable LTPS TFTS, 5000cycles of dynamic mechanical stress with tensile and perpendicular directions were applied with 2-mm bending radius. Based on the results, TFT reliability can be enhanced by controlled the crack position using the crack-guided passivation layer.