Low Temperature poly-Si Thin Film Research Articles

Threshold voltage uniformity improvement by introducing charge injection tuning for low-temperature poly-Si thin film transistors with metal/oxide/nitride/oxide/silicon structure

Low-temperature poly-Si thin film transistors (TFTs) with a metal/oxide/nitride/oxide/silicon structure were fabricated to investigate the feasibility of suppressing threshold voltage variations between TFTs. By applying relatively high positive and negative gate bias voltages, threshold voltage could be tuned positively and negatively, respectively, by injecting charges into the charge trap layer. Stability of threshold voltage against positive gate bias at a level close to the actual circuit operation was not degraded compared with the case of an as-fabricated TFT. A uniform threshold voltage distribution could be achieved in a preliminary test using 16 TFTs by converging threshold voltages with a target value by tuning the threshold voltage for each TFT.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The low temperature poly-Si thin-film transistors (LTPS TFTs) have been extensively applied in the AMLCD and AMOLED due to their high carrier’s mobility and driving currents, and the ability to integrate the driving circuits onto the same substrate. The main mechanisms causing the degradation of the LTPS TFTs under bias stress are: hot carrier effect and self-heating effect. In this study, the degradation and recovery phenomena of the LTPS TFTs stressed by the hot carrier effect conditions would be systematically investigated. The device structures used in this study are n-channel LTPS TFTs with different lengths of lightly doped drain (LDD).First, we simultaneously apply a small positive DC voltage, approximately the threshold voltage plus 1V (Vth+1= +3 V), to the gate terminal and a large positive DC voltage (+12 V) to the drain terminal of the LTPS TFTs with three different LDD’s lengths. These stressing conditions would cause the TFTs operated in the saturation region, so that the channel is pinched off. And the electrons would be accelerated by a large transverse electric field when they drift from the source terminal to the drain one. The energetic electrons would impact the lattices of the channel and the interface between the gate dielectric and the channel near the drain terminal, causing the defect states and electron-hole pair generation. Few of the carriers with enough energy to overcome the energy barrier of gate dielectric would be trapped by the defects in it. The hot carrier effect causes the degradation of the TFTs devices, including the decrease of ON current and carrier mobility and the increase of OFF current, but less degradation of the threshold voltage and subthreshold swing. After the bias stressing, the resting time is added to investigate the recovery phenomena. The difference in the amount of degradation and the location of defects would cause the different recovery ratio. After the end of bias stressing, all of the terminals are not applied with any voltages in the resting periods. The electrons and holes generated in the channel near the drain terminal would recombine, and the defect states generated by the hot carrier impact slightly reduce, which causes the recovery phenomena of the degraded transistors.Then, we apply a small AC voltage (0 ~ +3 V) to the gate terminal and a large positive DC voltage (+12 V) to the drain one at the same time. This mode of bias stressing conditions is closer to the real operating mode of the TFTs in the driving circuits. From the experimental data, it could be found that there is no significant difference in the degradation of the TFTs under different frequency of AC signals applied on the gate. But the recovery ratio tends to gradually increase as the frequency increasing.Finally, a small positive DC voltage (+3 V) is applied to the gate terminal, and a large AC voltage (0 ~ +12 V) to the drain one at the same time. From the experimental data, it could be found that with the increase of AC signal frequency, the degradation of the TFTs decreases, but the recovery ratio of the TFTs increases due to the reduction of the effective stressing time in one period. As compared to the results of all stressing conditions, the TFTs, both of the gate and drain terminals applied with DC voltages, exhibit the largest degradation ratio but the least recovery one. However, the TFTs, as the gate terminal applied with DC voltages and drain one with AC voltage, exhibit the less degradation ratio but the largest recovery one.

(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

The degradation and recovery phenomena of n-type LTPS TFTs stressed at hot carrier effect region under various bias conditions are investigated. The devices with longer LDD’s length demonstrate less degradation ratio but more recovery ratio, because of the lower transverse electric field. As the AC signals are applied to the gate terminal, the degradation of devices shows no significant dependence of AC signal frequency, but the recovery ratio displays the similar trends as AC signal frequency changing. However, as the AC signals are applied to the drain terminal, the degradation of devices shows very significant dependence of AC signal frequency. The higher the AC signal frequency is, the less degradation the devices show, but the recovery ratio displays the similar trends as AC signal frequency changing. From the results of all stressing conditions, the LTPS TFTs stressed with DC voltages exhibit the largest degradation ratio but almost the least recovery one.

Statistical Study of Degradation of Flexible Poly-Si TFTs Under Dynamic Bending Stress

Degradation of flexible low-temperature poly-Si thin film transistors (TFTs) under dynamic bending cycles is investigated with statistical method. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I_{\mathrm{ ON}}$ </tex-math></inline-formula> degradation data of different bending cycles and bending conditions are compared to five different statistical distribution models, and it is determined that the Gamma distribution best fits degradation data. Based on the model, the reliability of TFTs under a given stress condition can be evaluated under two typical application scenarios: (1) reliability prediction for large bending cycles; (2) reliability evaluation based on stress test with limited sample size.

Degradation and Failure of Flexible Low-Temperature Poly-Si TFTs Under Dynamic Stretch Stress

Degradation and failure behaviors of the flexible low-temperature poly-Si (LTPS) thin film transistors (TFTs) under repetitive stretch stress parallel to channel length (L) direction are investigated. A geometric effect is observed in degradation of the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ), which depends on the channel width (W) and active area ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WL</i> ), while has a weak correlation with L. Three failure modes of TFTs are identified from their I-V characteristics: damage in the gate insulator (GI), channel traps generation, and metal line cracks. Failure statistics show that the GI failure has a low failure rate and follows the exponential distribution, while the other two modes have high failure rates in the early stage of the stretch cycles, and their failure distributions follow the limited failure population (LFP) model.

Improvement of negative bias temperature instability of LTPS TFTs by high pressure H2O annealing

In this study, high pressure H2O annealing (HPA) was performed to improve the reliability of low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate. Due to the low heat resistance of the PI substrate, the pressure was high to reduce the temperature of the heat treatment. HPA was performed at 130 °C and 0.3 Mpa in an H2O ambient for 2 h. After HPA treatment, the threshold voltage (VT) shifted to the positive direction from −2.27 V to −1.75 V, and the hysteresis (ΔVT) decreased from 0.67 V to 0.24 V. The density of states (DOS) measurement shows that the interface trap decreased after HPA processing, hence, it is assumed that stability for bias stress has improved. Before and after HPA, the VT shift for negative bias temperature instability (NBTI) stress was 1.19 V and 0.2 V, respectively. After HPA treatment, ΔVT decreased significantly for bias stress. It seems that the decomposed oxygen from H2O diffused to the gate insulator and combined with Si to reduce the oxygen vacancy. The strength of the gate insulator improved after HPA.

Bias stress instability of LTPS TFTs on flexible substrate with activation annealing temperature

In this paper, we identified the defect state of p-channel low temperature poly-Si thin film transistors (LTPS TFTs) fabricated on a polyimide (PI) substrate that is distributed differently in the interface and channel areas depending on the activation annealing temperature, as well as observed the effect on the threshold voltage (VT) and reliability. To verify the effect of the process temperature on the performance of the LTPS TFTs, an activation heat treatment was conducted at 400 °C, 370 °C and 340 °C. More defects were distributed in the interface and channel area of LTPS TFTs with low heat treatment temperature, resulting in VT formed at a higher voltage. After the negative bias temperature instability (NBTI) test, the VT shifted in the negative voltage direction and moved −0.13 V, −0.51 V and −0.72 V from LTPS TFTs with high activation annealing temperature. In the hot carrier instability (HCI) test, VT also shifted to the negative direction of −0.19 V, −0.51 V, and −1.07 V. The defects distributed in the interface and channel areas that are not curated or activated due to the low activation annealing temperature caused instability under the bias stress.

Optimized Design of Carrier Injection Terminal for Reliable Low-Temperature Poly-Si TFTs Under Dynamic Hot-Carrier Stress

Dynamic hot-carrier (HC) degradation can be effectively suppressed in four-terminal low-temperature poly-Si (LTPS) thin film transistors (TFTs) with a carrier injection terminal. In order to enhance the reliability of the four-terminal LTPS TFTs, geometry effect of the carrier injection terminal, such as width and location, on the dynamic HC degradation is systematically studied. It shows that a wider carrier injection terminal, which provides more carriers injection, can suppress the degradation more effectively. As for the location, if the injection terminal is adjacent to the edge of the drain depletion region, which extends into the channel at the falling time of the gate voltage pulses, the four-terminal TFTs can provide the best immunity to the dynamic HC degradation. The proposed optimization scheme can greatly enhance the reliability of LTPS TFTs, and the mechanism can be understood based on the nonequilibrium p-n junction degradation model.

Effects of Channel Type and Doping on Hysteresis in Low-Temperature Poly-Si Thin-Film Transistors

The influence of channel type and doping on hysteresis in the current–voltage characteristics of poly-Si thin-film transistors (TFTs) has been investigated using p-/n- and intrinsic/B-doped channel TFTs. The hysteresis is greater in the p-channel than the n-channel and decreases in the p-channel but increases in the n-channel as the channel is doped with B. The energy profiles of the border trap density show asymmetry, in which the trap density is greater in the lower half of the bandgap. The border trap density increases as the channel is doped with B. The difference in border trap density between the near bandedge and near midgap energy levels is greater in the p-channel than the n-channel and decreases in the p-channel but increases in the n-channel as the channel is doped with B. The results show good agreement between the hysteresis effect and the energy profiles of border trap density.

Poly-Si TFTs integrated gate driver circuit with charge-sharing structure**Project supported by the Science and Technology Project of Hunan Province, China (No. 2015JC3401)

A p-type low-temperature poly-Si thin film transistors (LTPS TFTs) integrated gate driver using 2 non-overlapped clocks is proposed. This gate driver features charge-sharing structure to turn off buffer TFT and suppresses voltage feed-through effects. It is analyzed that the conventional gate driver suffers from waveform distortions due to voltage uncertainty of internal nodes for the initial period. The proposed charge-sharing structure also helps to suppress the unexpected pulses during the initialization phases. The proposed gate driver shows a simple circuit, as only 6 TFTs and 1 capacitor are used for single-stage, and the buffer TFT is used for both pulling-down and pulling-up of output electrode. Feasibility of the proposed gate driver is proven through detailed analyses. Investigations show that voltage bootrapping can be maintained once the bootrapping capacitance is larger than 0.8 pF, and pulse of gate driver outputs can be reduced to 5 μs. The proposed gate driver can still function properly with positive shift within 0.4 V and negative shift within −1.2 V and it is robust and promising for high-resolution display.

Ultrahigh-performance (100)-oriented polycrystalline silicon thin-film transistors and their microscopic crystal structures

A multiline beam continuous-wave laser lateral crystallization (MLB-CLC) method was developed to realize a predominantly (100)-oriented polycrystalline silicon (poly-Si) film with a high biaxial tensile strain. Low-temperature poly-Si (LTPS) thin film transistors (TFTs) with an ultrahigh maximum electron field effect mobility of 1010 cm2 V−1 s−1 were realized. The correlation between the performance and microscopic crystallinity of the TFTs was investigated. The performance enhancement of TFTs brings about highly (100)-surface-oriented large Si crystallites with a high biaxial tensile strain and grain boundaries being parallel to the current flow.

Charge-Trap Inactivation of Multi-Line-Beam Clc Poly-Si Tfts Using Channel Impurity Doping

Linearly-arranged long silicon crystal grains have been formed by using Multi-Line-Beam Continuous-wave laser Lateral Crystallization (MLB-CLC). Crystallinity of the laser-crystallized poly-Si thin film are biaxially oriented to (110)-(111)-(211) crystal orientation. The low-temperature poly-Si thin film transistors (LTPS-TFTs), however have a high-OFF leakage current and ON/OFF ratio become small. Charge traps on the long grain boundaries between source and drain would induce the high-OFF leakage current. In this work, we introduce a channel doping for inactivation of the traps, and high ON/OFF ratio is achieved. Poly-Si TFTs were fabricated as follows. Buffer SiO2 film (1 μm), a-Si (150 nm) and cap SiO2 (100 nm) were deposited on a quartz substrate. CW laser lateral crystallization with multi-line laser-beam spot was carried out on the a-Si films. The wavelength of the laser was 532 nm, and laser power and scan speed were 7.5 W and 0.5 cm/s, respectively. After the laser crystallization, the cap SiO2 was etched with buffered HF aqueous solution (BHF). In order to pattern the poly-Si active layer, lithography and dry etching (Cl2: 20 sccm, HBr: 20 sccm) were performed. Channel doping on channel region was carried out by boron (B) ions with 3 conditions (ion dose: 5×1012 cm-2, 7×1012 cm-2, 9×1012 cm-2, acceleration voltage: 19 keV). Gate SiO2 (42 nm) was deposited with ICP- CVD. Mo gate electrode (300 nm) was deposited by sputtering method. After resist patterning, the gate electrode was etched with an aqueous solution of H3PO4: HNO3: CH3COOH: H2O = 400: 25: 50: 25. A self-aligned S/D regions were formed by As ion doping (ion dose: 2×1015cm-2, acceleration voltage: 66 keV). Activation anneal was carried out at 550℃ in N2 ambient for 30 minutes. A sacrificial oxide layer in the S/D region was removed with BHF. After the removal, interlayer SiO2 film was deposited with APCVD. Contact holes were formed on the APCVD interlayer dielectric film with BHF. Mo metal pad was deposited by sputtering method, and finally the samples were sintered at 400°C in H2 ambient for 30 minutes. The IDS - VGS characteristic of the fabricated poly-Si TFTs are shown in Fig.1. As the boron impurity concentration increased, the off-leakage current was reduced. It is considered that boron impurity compensated the defect traps in the channel region. At the concentration of 1.3×1020 cm-3, the off leakage current at Vg=0 V was 3×10-11 A and ON/OFF ratio was 106. ON current was reduced by introducing the channel impurity. The electron field-effect mobilities for the boron impurities of 7.1×1019 cm-3, 1.0×1020 cm-3 and1.3×1020 cm-3 were 398, 333, and 261 cm2/Vs, respectively. By introducing boron impurity, the Coulomb scattering was occurred and the electron mobility was reduced. Figure 1

Characterization of (100)-Dominantly Oriented Poly-Si Thin Film Transistors Using Multi-Line Beam Continuous-Wave Laser Lateral Crystallization

Low-temperature poly-Si thin film transistors with high mobility and uniformity have been required for high resolution flat panel display (FPD) technology. In this work, we succeeded in controlling orientation of poly-Si film by using multi-line beam (MLB) continuous-wave laser lateral crystallization (CLC) with overlapping and (100)-dominantly oriented poly-Si film was realized. Si crystal grains were developed along laser scanning direction with an average grain size of approximately 20 μm x 2 μm. The adjacent Si crystal grains had almost identical orientation in the space with misorientation angle of under 15o. The fabricated TFTs have high field effect mobility up to 1010 cm2/Vs. Moreover, device characteristics of the fabricated TFTs were investigated and mobility variation was evaluated.

Crystallinity Evaluation of Low Temperature Polycrystalline Silicon Thin Film Using UV/Visible Raman Spectroscopy

Low temperature poly-Si (LTPS) is one of the most important high mobility channel materials for thin film transistors (TFTs). However, the improvement of the LTPS TFT performance is limited by the grain size and crystallinity variation. Thus, advanced nondestructive and high-resolution evaluation techniques are needed for LTPS thin film to monitor its crystallinity and grain size distribution. We evaluated the crystallinity of LTPS thin film during the fabrication process with various conditions using UV/visible Raman spectroscopy. As a result, we confirmed from Raman imaging measurements that a-Si deposited at higher temperature and lower pressure is crystallized rapidly. It can be considered that slow crystallization is caused by strong tensile strain and high hydrogen concentration in LTPS thin films. Furthermore, good crystallinity can be obtained with increasing annealing duration and deposition temperature of a-Si. In conclusion, we believe Raman spectroscopy, especially when used as imaging technique, is useful for in-line process evaluation.

Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization

Highly biaxially oriented linearly arranged poly-Si thin films were formed by double line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and energetically stable Σ3 grains boundary were observed dominantly. Silicon grains were elongated in the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were fabricated. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low temperature (≦550 o C) by a metal gate self-aligned process.The TFTs were fabricated as follows. A-Si of 150 nm thickness and cap SiO2 of 100 nm thickness were deposited on a quartz substrate. CW laser crystallization with double-line spot irradiation (wavelength: 532 nm, laser power: 8.5 W, scan speed: 0.25 cm/s) on a-Si was carried out, and lateral-crystallized poly-Si was formed. After the laser crystallization, the cap SiO2 was etched using buffered HF aqueous solution (BHF), and lithography and dry etching (Cl2: 40 sccm, HBr: 40 sccm) were performed in order to pattern the poly-Si active layer. Next, gate SiO2 of 50 nm thickness was deposited by inductively coupled plasma chemical vapor deposition (ICP CVD, SiH4: 0.6 sccm, O2: 10 sccm, Ar: 40 sccm) and a Mo gate electrode of 200 nm thickness was deposited by sputtering method. After lithography patterning, wet etching of Mo was carried out with a solution of H3PO4: HNO3: CH3COOH: H2O= 400: 25: 50: 25 and the gate electrode was formed. A self–aligned source and drain system was formed by As ion doping (ion dose: 2×1015 cm-2, acceleration voltage: 66 keV) using the Mo gate electrode as the mask. Activation annealing treatment was carried out at 550o C in N2 ambient for 30 min. A sacrificial oxide layer in the S/D region was removed using BHF. After the removal, 150-nm-thick interlayer insulation films were deposited by atmospheric pressure chemical vapor deposition (APCVD), and the contact hole was etched using BHF. A Mo metal pad was deposited by sputtering method, and finally sintering processing was carried out at 400 o C in H2ambient for 30 min. Figure 1 shows a microphotograph of the fabricated DLB-CLC poly-Si TFT.A TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. At the electron field effect mobility, its variation was within 10% at same crystallization region. High-performance TFTs with DLB-CLC were demonstrated, however it was found that off-leakage current was relatively large. The leakage current mechanism was investigated by measuring temperature dependence of the TFT characteristics. The field-effect mobilities at the ON region were proportional to T-1.5 as shown in Fig. 2. The result shows the phonon scattering was dominant as same as single silicon crystal. On the other hand, in the OFF region, the electrical conductivity shows logarithmic behavior as a function of exp{-EB/kBT} as shown in Fig. 3. This leakage current shows that there are many trap states in the grain boundaries.

Characteristics of Poly-Si Thin Film Transistors with Highly Biaxially Oriented Linearly Arranged Poly-Si Thin Films Using Double Line Beam Continuous-Wave Laser Lateral Crystallization

Highly biaxially oriented linearly arranged poly-Si thin films were formed by double-line beam continuous-wave laser lateral crystallization (DLB-CLC). Crystallinities of the poly-Si thin films were (110), (111), and (211) for the laser scan, transverse, and surface directions, respectively, and an energetically stable Σ3 grain boundary was dominantly observed. Silicon grains were elongated along the laser scan direction and one-dimensionally very large silicon grains with lengths of more than 100 µm were formed. High-performance low-temperature poly-Si thin film transistors (TFTs) using these poly-Si thin films were fabricated at low-temperatures (≦550゜C) by a metal gate self-aligned process and a TFT with a high electron field effect mobility of µFE= 560 cm2V-1s-1 in a linear region was realized. Also, electron field effect mobility variation of below 10% was obtained at the same crystallization region. Leakage current mechanism was also investigated by temperature dependence of the TFT characteristics.

The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors

Low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have a high carrier mobility that enables the design of small devices that offer large currents and fast switching speeds. However, the electrical characteristics of the conventional self-aligned polycrystalline silicon (poly-Si) TFTs are known to present several undesired effects, such as large leakage currents, the kink effect, and the hot-carrier effect. For this paper, LTPS TFTs were fabricated, and the SiN x /SiO 2 gate dielectrics and the effect of the gate-overlap lightly doped drain (GOLDD) were analyzed in order to minimize these undesired effects. GOLDD lengths of 1, 1.5 and 2 μm were used, while the thickness of the gate dielectrics (SiN x /SiO 2) was fixed at 65 nm (40 nm/25 nm). The electrical characteristics show that the kink effect is reduced in the LTPS TFTs using a more than 1.5 μm of GOLDD length. The TFTs with the GOLDD structure have more stable characteristics than the TFTs without the GOLDD structure under bias stress. The degradation from the hot-carrier effect was also decreased by increasing the GOLDD length. After applying the hot-carrier stress test, the threshold voltage variation (Δ V TH) was decreased from 0.2 V to 0.06 V by the increase of the GOLDD length. The results indicate that the TFTs with the GOLDD structure were protected from the degradation of the device due to the decreased drain field. From these results it can be seen that the TFTs with the GOLDD structure can be applied to achieve high stability and high performance in driving circuit applications for flat-panel displays.

Degradation of n-channel low temperature poly-Si TFTs dynamically stressed in OFF region with positive drain bias

The degradation characteristics of n-channel low temperature poly-Si thin film transistors (LTPS TFTs), which are alternately stressed in OFF region with drain positively biased and source grounded, are investigated. In this research, rectangular pulse signals, dynamically changing from −18 to 0 V with varied parameters such as rising time, falling time, and frequency, are applied to the gate terminal, and the drain is simultaneously biased at +5 V to stress the LTPS TFTs and examined the deterioration. It is observed that the degradation strongly depends on the frequency and rising time rather than the falling time of AC signals. As the gate voltage transitionally changes in the rising period, the accumulated holes should be swept out and flow into the source terminal, resulting from the drain with positively biased and the floating body structure of TFTs. A degradation model of the parasitic BJT, based on the flowing direction of a sampling current I d, is proposed to explain the degradation mechanism of LTPS TFTs, and demonstrated by two electrical measurements, C–V curves and saturated forward and reverse I d– V g transfer curves.

The Reliability of LTPS-TFTs Alternately Stressed in OFF Region

The reliability of n-channel low temperature poly-Si thin film transistors (LTPS TFTs), which are dynamically stressed in OFF region with drain zero biased and source grounded, is investigated. Rectangular pulses with different parameters such as rising time, falling time or frequency are imposed to the gate electrode to examine the degradation. It is observed that the degradation depends strongly on the rising time and frequency of ac signal. As the gate voltage switches in the rising period, the accumulated holes should be swept out and flow into source or drain terminals, owing to the floating body structure of TFTs. Therefore, there is high electric field at the rising period of transient stress, which enhances the degradation. A degradation model is proposed to explain the degradation mechanism of LTPS TFTs on the basis of the flowing direction of the sampling current Id, and demonstrated by two electrical measuring items, saturation forward & reverse Id-Vg transfer curves and C-V curves.

Embedded nonvolatile memory devices with various silicon nitride energy band gaps on glass used for flat panel display applications

Nonvolatile memory (NVM) devices with a nitride–nitride–oxynitride stack structure on a rough poly-silicon (poly-Si) surface were fabricated using a low-temperature poly-Si (LTPS) thin film transistor technology on glass substrates for application of flat panel display (FPD). The plasma-assisted oxidation/nitridation method is used to form a uniform oxynitride with an ultrathin tunneling layer on a rough LTPS surface. The NVMs, using a Si-rich silicon nitride film as a charge-trapping layer, were proposed as one of the solutions for the improvement of device performance such as the program/erase speed, the memory window and the charge retention characteristics. To further improve the vertical scaling and charge retention characteristics of NVM devices, the high-κ high-density N-rich SiNx films are used as a blocking layer. The fabricated NVM devices have outstanding electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low subthreshold swing, a low operating voltage of less than ±9 V and a large memory window of 3.7 V, which remained about 1.9 V over a period of 10 years. These characteristics are suitable for electrical switching and data storage with in FPD application.