(Digital Presentation) Degradation and Recovery of Low Temperature Poly-Si Thin Film Transistors Under DC and AC Bias Stresses

Abstract

The low temperature poly-Si thin-film transistors (LTPS TFTs) have been extensively applied in the AMLCD and AMOLED due to their high carrier’s mobility and driving currents, and the ability to integrate the driving circuits onto the same substrate. The main mechanisms causing the degradation of the LTPS TFTs under bias stress are: hot carrier effect and self-heating effect. In this study, the degradation and recovery phenomena of the LTPS TFTs stressed by the hot carrier effect conditions would be systematically investigated. The device structures used in this study are n-channel LTPS TFTs with different lengths of lightly doped drain (LDD).First, we simultaneously apply a small positive DC voltage, approximately the threshold voltage plus 1V (Vth+1= +3 V), to the gate terminal and a large positive DC voltage (+12 V) to the drain terminal of the LTPS TFTs with three different LDD’s lengths. These stressing conditions would cause the TFTs operated in the saturation region, so that the channel is pinched off. And the electrons would be accelerated by a large transverse electric field when they drift from the source terminal to the drain one. The energetic electrons would impact the lattices of the channel and the interface between the gate dielectric and the channel near the drain terminal, causing the defect states and electron-hole pair generation. Few of the carriers with enough energy to overcome the energy barrier of gate dielectric would be trapped by the defects in it. The hot carrier effect causes the degradation of the TFTs devices, including the decrease of ON current and carrier mobility and the increase of OFF current, but less degradation of the threshold voltage and subthreshold swing. After the bias stressing, the resting time is added to investigate the recovery phenomena. The difference in the amount of degradation and the location of defects would cause the different recovery ratio. After the end of bias stressing, all of the terminals are not applied with any voltages in the resting periods. The electrons and holes generated in the channel near the drain terminal would recombine, and the defect states generated by the hot carrier impact slightly reduce, which causes the recovery phenomena of the degraded transistors.Then, we apply a small AC voltage (0 ~ +3 V) to the gate terminal and a large positive DC voltage (+12 V) to the drain one at the same time. This mode of bias stressing conditions is closer to the real operating mode of the TFTs in the driving circuits. From the experimental data, it could be found that there is no significant difference in the degradation of the TFTs under different frequency of AC signals applied on the gate. But the recovery ratio tends to gradually increase as the frequency increasing.Finally, a small positive DC voltage (+3 V) is applied to the gate terminal, and a large AC voltage (0 ~ +12 V) to the drain one at the same time. From the experimental data, it could be found that with the increase of AC signal frequency, the degradation of the TFTs decreases, but the recovery ratio of the TFTs increases due to the reduction of the effective stressing time in one period. As compared to the results of all stressing conditions, the TFTs, both of the gate and drain terminals applied with DC voltages, exhibit the largest degradation ratio but the least recovery one. However, the TFTs, as the gate terminal applied with DC voltages and drain one with AC voltage, exhibit the less degradation ratio but the largest recovery one.