Low Subthreshold Slope Research Articles

High-performance electrolyte-gated amorphous InGaZnO field-effect transistor for label-free DNA sensing

Accurate, convenient, label-free, and cost-effective biomolecules detection platforms are currently in high demand. In this study, we showcased the utilization of electrolyte-gated InGaZnO field-effect transistors (IGZO FETs) featuring a large on-off current ratio of over 106 and a low subthreshold slope of 78.5 mV/dec. In the DNA biosensor, the modification of target DNA changed the effective gate voltage of IGZO FETs, enabling an impressive low detection limit of 0.1 pM and a wide linear detection range from 0.1 pM to 1 μM. This label-free detection method also exhibits high selectivity, allowing for the discrimination of single-base mismatch. Furthermore, the reuse of gate electrodes and channel films offers cost-saving benefits and simplifies device fabrication processes. The electrolyte-gated IGZO FET biosensor presented in this study shows great promise for achieving low-cost and highly sensitive detection of various biomolecules.

Fully Printed Negative-Capacitance Field-Effect Transistors with Ultralow Subthreshold Swing and High Inverter Signal Gain.

The switching of conventional field-effect transistors (FETs) is limited by the Boltzmann barrier of thermionic emission, which prevents the realization of low-power electronics. In order to overcome this limitation, among others, unconventional device geometry with a ferroelectric/dielectric insulator stack has been proposed to demonstrate stable negative-capacitance behavior. Here, the switching of the ferroelectric layer behaves like a step-up amplifier and results in a body factor less than 1. This implies a larger change in the semiconductor surface potential compared to the applied gate voltage variation. The transistors with such ferroelectric/dielectric stack are known as negative-capacitance field-effect transistors (nc-FETs), and can demonstrate a subthreshold slope lower than the Boltzmann's limit (60 mV/decade). While nc-FETs have typically been realized with high-vacuum-deposition processes, here we show fully printed nc-FETs with amorphous indium-gallium-zinc oxide (a-IGZO) as the semiconductor material, Al2O3 as the dielectric, and poly(vinylidene fluoride-trifluoroethylene) (PVDF-TrFE) as the polymer ferroelectric. The printed nc-FETs demonstrate an extremely low subthreshold slope of ∼2.3 mV/decade at room temperature, which remains below the Boltzmann's limit for over 5 orders of magnitude of drain currents. Furthermore, the unipolar depletion-load-type inverters fabricated using n-type nc-FETs have demonstrated an extraordinary signal gain of 2691.

Comprehensive characterization of a high‐performance double heterojunction InGaAs pHEMT for linear power‐efficient amplifiers applications

AbstractThis article centers its attention on the phenomenon of electrostatics, linearity, analogue, and RF performance of a 0.5 μm × (2 × 100) μm double heterojunction AlGaAs/InGaAs/GaAs pHEMT using on‐wafer DC and RF measurements up to 50 GHz. With a high ION/IOFF ratio (1.21 × 107) and low subthreshold slope (72.7 mV/dec), a flat and high transconductance over a wide range of Vgs has been achieved for the tested device. Furthermore, the input intercept and higher‐order voltage intercept point both attained large values with low intermodulation and harmonic distortion. Regarding RF parameters, the intrinsic gain has been achieved up to 28 dB. The GBW up to 750 GHz was attained, with the highest fT and fmax values being 24.5 GHz and 99.3 GHz, respectively. Since the device has very low intrinsic capacitance, parameters like TFP, GFP, and GTFP also showed excellent results. The high intrinsic gain and TGF indicate ample potential of the device for use as an amplifier. Investigating the parameters reveals the device to have very good linearity and amplifying capability.

Design and Implementation of Silicon-Doped Ferrogate Stacking JL-VTFET in MIC Sepic Convertor

This paper introduces a Ferro technique in the junctionless vertical tunnel field effect transistor in which the ferroelectric property in the [Formula: see text] is developed with the help of Silicon doping in it. The incorporation of the ferroelectric oxide stacking with [Formula: see text] results in low sub-threshold slope and high trans-conductance which is highly suitable for sensing of small voltage and converting it into strong drain current. The introduction of the high k-dielectric material with [Formula: see text] also leads to small lattice mismatch so that the losses can be reduced. The device shows ON current in the order of (2.62 × 10[Formula: see text]A/[Formula: see text]m) and the ratio of the ON to OFF drain current is noted as (of 2.031 × 10[Formula: see text]). Moreover, the device exhibits sub-threshold slope 35mV/dec and the ratio of trans-conductance to drain current (gm/[Formula: see text]) in the range of 150–350 V[Formula: see text]. Then the design structure is used to develop the circuit of multiple input converters (MIC) because the device shows high conversion rate (trans-conductance). For the converter, State-space analysis is used for the modeling of converter which was further followed with the design of converters’ energy storing apparatus with its voltage gain formulation. Interaction analysis is used to create a decentralized controller. The controllers’ robustness is tested using parametric uncertainty. A 175-watt experimental archetype with 36 volt and 24-volt sources is developed in the lab. The digital controller was implemented using the processor. The efficacy of controllers for regulating sources and loads has been verified. The controller’s strength is ensured by the satisfactory correlation between simulation and investigational results. For the result outcome one can validate Silicon Doped Ferro Gate Stacking JL-VTFET results for low power applications.

High Mobility Amorphous Polymer‐Based 3D Stacked Pseudo Logic Circuits through Precision Printing

AbstractDirect printing of conjugated polymer thin‐film transistors enables the fabrication of deformable devices with low cost, high throughput, and large area. However, a relatively poor device performance of printed devices remains a major obstacle to their application in high‐end display backplanes and integrated circuits. In this study, high‐performance and highly stackable printed organic transistors is developed, arrays, and circuits using a near‐amorphous polymer, indacenodithiophene‐co‐benzothiadiazole (IDT‐BT). The printed devices exhibited high saturation mobility (>1 cm2 V−1 s−1), high on/off ratio (>107), and low subthreshold slope (245 mV dec−1). In addition, 16 × 16 printed IDT‐BT arrays achieved 100% fabrication yield, with excellent device‐to‐device uniformity and low variations of mobility (9.55%) and threshold voltage (4.51%), and good operational and environmental stability (>365 days). Furthermore, five stacked 3D transistors are demonstrated with an excellent 3D uniformity without compromising device performance due to a low required thermal budget for processing amorphous IDT‐BT. Finally, a new concept of 3D universal logic gate with high voltage gain (33.91 V/V) and record density (100 printed transistors per cm2) is proposed and fabricated, which is relevant for the commercialization of low‐cost printed display backplanes and high‐density integrated circuits based on highly processable polymeric semiconductors.

Atomic Layer Deposition of WO3-Doped In2O3 for Reliable and Scalable BEOL-Compatible Transistors.

Tungsten oxide (WO3) doped indium oxide (IWO) field-effect transistors (FET), synthesized using atomic layer deposition (ALD) for three-dimensional integration and back-end-of-line (BEOL) compatibility, are demonstrated. Low-concentration (1∼4 W atom %) WO3-doping in In2O3 films is achieved by adjusting cycle ratios of the indium and tungsten precursors with the oxidant coreactant. Such doping suppresses oxygen deficiency from In2O2.5 to In2O3 stoichiometry with only 1 atom % W, allowing devices to turn off stably and enhancing threshold voltage stability. The ALD IWO FETs exhibit superior performance, including a low subthreshold slope of 67 mV/decade and negligible hysteresis. Strong tunability of the threshold voltage (Vth) is achieved through W concentration tuning, with 2 atom % IWO FETs showing an optimized Vth for enhancement-mode and a high drain current. ALD IWO FETs have remarkable stability under bias stress and nearly ideal performance extending to sub-100 nm channel lengths, making them promising candidates for high-performance monolithic 3D integrated devices.

Enabling of CMOS Circuit using Dual Material Gate Germanium Pocket Induced FDSOI MOSFET

This research presents a comparison of the electrical performance of a double-side induced germanium-pocket (IGP) FD-SOI MOSFET and a dual material gate IGPFDSOI (DIGPFDSOI). The electrical performance is reviewed by comparing the device parameters like drain current, band diagram, lateral electric field, surface potential, and work function of the gate material. The proposed structure exhibits excellent characteristics compared to the IGPFDSOI MOSFET. The proposed structure has a greater Ion/Ioff ratio, a lower subthreshold slope, reduced capacitance, and an elevated cut-off frequency. The implementation of a dual metal gate is considered a superior method in comparison to FD-SOI technology because it effectively reduces the negative effects of scaling. A study is being done to analyze the differences in the work functions of metal gates to evaluate the effectiveness of the proposed construction. The comparison evaluation shows that the suggested design can be used for both digital and analog tasks because it has a higher switching frequency and a better cut-off frequency. Apart from this, the proposed structure can also be implemented without making substantial changes to the conventional FD-SOI MOSFET fabrication process flow. Here, we are using n-type and p-type DIGPFDSOI MOSFETs to make a CMOS converter circuit. Sentaurus TCAD is used to simulate and analyze the performance of the proposed structure.

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC.

Development of Schottky barrier field-effect transistors (SB-MOSFET) with ultra-low thermal budget

This work presents the development of SB-MOSFET transistors incorporating thin HfO2 as a thin gate dielectric deposited by thermal atomic layer deposition (ALD) at low temperature. Aluminum thin films were used as the source/drain (S/D) and gate (G) electrodes, using e-beam evaporation at high-vacuum conditions. Even though low subthreshold slope (SS) values of 111 mV/dec and threshold voltage (Vth) of 0.58 V were obtained using a low thermal budget of 150 °C for transistor fabrication, scanning electron microscopy (SEM) analysis highlights the importance of proper mask alignment in order to enhance electrical performance and thus, reproducibility of the electrical characteristics of this device. This device can be fully integrated into silicon after standard Complementary Metal-Oxide-Semiconductor (CMOS)-compatible processing, so that it could be easily adopted into Front-End-Of-Line or even in Back-End-Of-Line stages of an integrated circuit, where low thermal budget is required and where its functionality could be increased by developing additional and fast logic.

Impact of Nanowire Radius and Channel Thickness with High-k Gate Dielectric in GAA-JLT

As the transistor’s size becomes smaller, degradation in the short-channel effects (SCEs) becomes more apparent. This leads to research work on multi-gate transistors such as the Fin-Field Effect Transistor (FinFET) and Gate-All-Around (GAA) transistor, where the 3D architecture have been shown to have superior performance as compared to conventional planar transistor. Transistor without junctions (JLT) which realizes a single type of doping has also been gaining popularity for biosensor applications due to its superior electrostatic performances in terms of Drain-Induced Barrier Lowering (DIBL), off-state leakage current (Ioff) and Subthreshold Slope (SS). In this work, the impact of changes in parameters such as the gate oxide material, nanowire radius and channel thickness toward the performance of a Gate-all-around JLT (GAA-JLT) have been studied using TCAD simulator. It was found that smaller nanowire radius and thicker channel produces lower DIBL, Ioff and SS, with the use of HfO2 as gate oxide materials shows better results than Si3N4. Meanwhile, the impact of parameters variations seemed to be negligible on the on-state current (Ion). The outcome of this work can be used as a basis to understand the impact of structural parameters variations towards the performance of a more complex GAA-JLT structure.

Low temperature passivation of silicon surfaces for enhanced performance of Schottky-barrier MOSFET

By using a simple device architecture along with a simple process design and a low thermal-budget of a maximum of 100 °C for passivating metal/semiconductor interfaces, a Schottky barrier MOSFET device with a low subthreshold slope of 70 mV dec−1 could be developed. This device is enabled after passivation of the metal/silicon interface (found at the source/drain regions) with ultra-thin SiO x films, followed by the e-beam evaporation of high- quality aluminum and by using atomic-layer deposition for HfO2 as a gate oxide. All of these fabrication steps were designed in a sequential process so that a gate-last recipe could minimize the defect density at the aluminum/silicon and HfO2/silicon interfaces, thus preserving the Schottky barrier height and ultimately, the outstanding performance of the transistor. This device is fully integrated into silicon after standard CMOS-compatible processing, so that it could be easily adopted into front-end-of-line or even in back-end-of-line stages of an integrated circuit, where low thermal budget is required and where its functionality could be increased by developing additional and fast logic.

High performance junctionless FDSOI SiGe channel p-FinFET with high ION/IOFF ratio and excellent SS

This paper presents a novel FDSOI FinFETs with SiGe channel/Si cap layer (35 nm/5 nm) formed on SOI wafers with 20 nm Si body. Electrical characterization result shows that JL FDSOI FinFETs with SiGe channel exhibited low subthreshold slope (SS) of 86 mV/decade and record high ON-OFF current ratio (ION/IOFF = 2 × 106) at VD = -0.5V, respectively. Device performance improvement was mainly attributed to high-epitaxial quality compressive strained SiGe channel and novel device structure. The strain in the channel of the transistors was estimated locally in TEM using Nano beam diffraction (NBD) technique. The FDSOI FinFET with SiGe channel, lays the foundation for the further development of high speed, high density, low cost, and 3D monolithic integration circuits.

Improved Dielectrically Modulated Quad Gate Schottky Barrier MOSFET Biosensor.

A novel Schottky barrier MOSFET with quad gate and with source engineering has been proposed in this work. A high-κ dielectric is used at the source side of the channel, while SiO2 is used at the drain side of the channel. To improve the carrier mobility, a SiGe pocket region is created at the source side of the channel. Physical and electrical characteristics of the proposed device are compared with conventional double gate Schottky barrier MOSFET. It has been observed that the proposed device exhibits better performance, with a higher ION/IOFF ratio and lower subthreshold slope. The high-κ dielectric, along with the SiGe pocket region, improves tunneling probability, while aluminum, along with SiO2 at the drain side, broadens the drain/channel Schottky barrier and reduces the hole tunneling probability, resulting in a reduced OFF-state current. Further, the proposed device is used as a biosensor to detect both the charged and neutral biomolecules. Biosensors are made by creating a nanocavity in the dielectric region near the source end of the channel to capture biomolecules. Biomolecules such as streptavidin, biotin, APTES, cellulose and DNA have unique dielectric constants, which modulates the electrical parameters of the device. Different electrical parameters, viz., the electric field, surface potential and drain current, are analyzed for each biomolecule. It has been observed that drain current increases with the dielectric constant of the biomolecules. Furthermore, the sensitivity and selectivity of the proposed biosensors is better than that of conventional biosensors made using double gate Schottky barrier MOSFETs. Sensitivity is almost twice that of a conventional sensor, while selectivity is six to twelve times higher than a conventional one.

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

Modeling and Performance Analysis of a Split-Gate T-Shape Channel DM DPDG-TFET Label-Free Biosensor

This article proposes, for the first time, a split-gate T-shape channel dielectrically modulated (DM) double-gate TFET (DGTFET) with a drain pocket (DP). This device can be used as a label-free biosensor. The analytical model for DM DPDG-TFET has been developed and it has been validated against commercial simulation software (Silvaco TCAD). This article intends to focus both on the sensitivity of the biosensor and its performance as a tunnel field-effect transistor (TFET) device. This has been accomplished by improvisations in the channel shape. The performance of the device has thoroughly been investigated in terms of threshold voltage, subthreshold slope, ON current, and OFF current. Due to the novel design, the proposed TFET possesses higher sensitivity, higher <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{ {\text{ON}}}/{I}_{ {\text{OFF}}}$ </tex-math></inline-formula> current ratio, and lower subthreshold slope. The inclusion of DP at the drain–channel junction proves to be a successful way to remove the ambipolarity completely. The high ON current without any ambipolarity has been achieved by optimizing the DP length and its doping concentration. The proposed T-shape DM DPDGTFET proves itself to be superior to several reported devices in terms of both biosensor as well as field-effect transistor (FET) device. The presence and absence of charge of various biomolecules are taken into consideration for evaluation of device sensitivity as a label-free biosensor.

Stacked printed MoS2 and Ag electrodes using electrohydrodynamic jet printing for thin-film transistors

Transition metal dichalcogenide-based thin-film transistors (TFTs) have drawn intense research attention, but they suffer from high cost of materials and complex methods. Directly printed transistors have been in the limelight due to low cost and an environmentally friendly technique. An electrohydrodynamic (EHD) jet printing technique was employed to pattern both MoS2 active layer and Ag source and drain (S/D) electrodes. Printed MoS2 lines were patterned on a silicon wafer using a precursor solution and simple annealing, and the patterns were transferred on other SiO2 substrates for TFT fabrication. On top of the patterned MoS2, Ag paste was also patterned for S/D electrodes using EHD jet printing. The printed TFTs had a high on–off current ratio exceeding 105, low subthreshold slope, and better hysteresis behavior after transferring MoS2 patterns. This result could be important for practical TFT applications and could be extended to other 2D materials.

Steep-Slope Transistor with an Imprinted Antiferroelectric Film.

The effect of negative capacitance (NC), which can internally boost the voltage applied to a transistor, has been considered to overcome the fundamental Boltzmann limit of a transistor. To stabilize the NC effect, the dielectric (DE) must be integrated into a heterostructure with a ferroelectric (FE) film. However, in a multidomain hafnia, the charge boosting effect is reduced owing to a lowering of the depolarization field originating from the stray field at each domain, and simultaneously, the operating voltage increases owing to the voltage division at the DE. Here, we demonstrate core approaches to the gate stack of energy-efficient device technology using a transient NC. Electrical measurements of the transistor with imprinted antiferroelectric and high CDE/CFE structures exhibit low subthreshold slopes below 20 mV/dec, a low voltage operation of 0.5 V, a fast operation of 20 ns, hysteresis-free Id-Vg, and high endurance characteristics of 1012 cycles. We expect that this will lead to the rapid implementation of the NC effect in high-speed switching device applications with significantly improved energy efficiency.

FinFET-based non-linear analog signal processing modules

FinFETs exhibit far superior transistor characteristics (better gate control and a lower sub-threshold slope) as compared to the standard MOSFETs, this paper first employs the FinFETs in the design of an operational transconductance amplifier (OTA). The FinFET-based OTA offers a linearity range and - 3 dB bandwidth of ± 300 mV and 631.81 GHz, respectively. Further, the non-linear applications of the proposed OTA, viz. voltage divider, memristor emulator, and a memristive neuron, are presented. The proposed analog voltage divider circuit contains one OTA and two external N-FinFETs. The maximum bandwidth obtained for the voltage divider is 217.54 GHz. The memristor emulator contains one OTA, two external N-FinFETs, and one grounded capacitor. The proposed emulator circuit follows the signature characteristics of the actual memristor device. The frequency response characteristics of the proposed emulator circuit depict a bandwidth of 22.7 GHz. The proposed emulator shows non-volatile as well as electronically tunable features. Next, Monte-Carlo simulation analysis has been performed on the proposed circuits in order to observe the effects of statistical variation in different operating conditions. Furthermore, we propose a FinFET-based passive memristive neuron model using a memristor emulator circuit. The proposed neuron circuit follows a tangent hyperbolic activation function. All the proposed circuits are suitable for monolithic implementation. The proposed circuits are verified using 20 nm FinFET technology. The simulation results obtained using HSPICE agree well with the theoretical analysis.

A steep switching WSe2 impact ionization field-effect transistor

The Fermi-Dirac distribution of carriers and the drift-diffusion mode of transport represent two fundamental barriers towards the reduction of the subthreshold slope (SS) and the optimization of the energy consumption of field-effect transistors. In this study, we report the realization of steep-slope impact ionization field-effect transistors (I2FETs) based on a gate-controlled homogeneous WSe2 lateral junction. The devices showed average SS down to 2.73 mV/dec over three decades of source-drain current and an on/off ratio of ~106 at room temperature and low bias voltages (<1 V). We determined that the lucky-drift mechanism of carriers is valid in WSe2, allowing our I2FETs to have high impact ionization coefficients and low SS at room temperature. Moreover, we fabricated a logic inverter based on a WSe2 I2FET and a MoS2 FET, exhibiting an inverter gain of 73 and almost ideal noise margin for high- and low-logic states. Our results provide a promising approach for developing functional devices as front runners for energy-efficient electronic device technology.

Low-power double-gate MoS2 negative capacitance transistors with near-zero DIBL

Negative capacitance (NC) devices hold great promise for improving subthreshold slope (SS). However, the theoretical exploration of the short-channel effect in NC and two-dimensional (2D) materials remains an ongoing challenge in device scaling. The present work demonstrates a double-gate MoS2 negative capacitance field-effect transistor (MoS2 DG-NCFET) with low power and near-zero drain-induced barrier lowering (DIBL) by exploring its design space considering the impact of various MoS2 layers, with the aid of the developed 2D short-channel model containing the NC effect and numerical simulation. The proposed monolayer MoS2 DG-NCFET model is solved by unifying the long and short channel models coupled with the one-dimensional Landau-Khalatnikov equation. The study indicates that a lower SS, considerable voltage saving (), and even the ability to achieve zero DIBL are seen in monolayer MoS2 devices when compared with those of non-2D MoS2, due to the combination of the atomic-scale thickness of channels and the double-gate structure. This study provides an insight for further reducing the feature size of ultralow power transistors.