Low Subthreshold Slope Research Articles

Ultrathin tin sulfide field-effect transistors with subthreshold slope below 60 mV/decade

In this paper, we present for the first time a field-effect-transistor (FET) having a 10 nm thick tin sulfide (SnS) channel fabricated at the wafer scale with high reproducibility. SnS-based FETs are in on-state for increasing positive back-gate voltages up to 6 V, whereas the off-state is attained for negative back-gate voltages not exceeding −6 V, the on/off ratio being in the range 102–103 depending on FET dimensions. The SnS FETs show a subthreshold slope (SS) below 60 mV/decade thanks to the in-plane ferroelectricity of SnS and attaining a minimum value SS = 21 mV/decade. Moreover, the low SS values can be explained by the existence of a negative value of the capacitance of the SnS thin film up to 10 GHz (for any DC bias voltage between 1 and 5 V), with the minimum value being −12.87 pF at 0.1 GHz.

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

In recent years, Ge-based group-IV alloys (GeSn, SiGeSn) have received a significant amount of attention as candidates to replace Silicon for future low power and high performance nanoelectronics [1]. The interest in these materials stems primarily from the fact that, by varying the Sn-content of the alloy, it is possible to precisely tune its bandgap from indirect to direct [2], which even opens up the possibility to switch the carrier transport from larger mass low mobility L-valley electrons to the lower mass and high mobility Γ-valley electrons. Adding Si atoms into GeSn alloys enables additional strain engineering by decoupling the lattice constant from the band gap and enables the fabrication of devices to target specific applications. Ge exhibits superior hole mobility over Si and GeSn is predicted to further improve carrier mobilities for both electrons and holes, while still retaining Si CMOS compatibility [3]. In this , we present the fabrication and characterization of Ge- and GeSn-based vertical gate-all-around (GAA) nanowire (NW) p-MOSFETs. Multilayer stacks of Ge and GeSn were grown on a Ge virtual substrate (Ge-VS) using industrial CVD reactors and subsequently characterized, confirming the high quality of the alloys.On these GeSn/Ge heterostructures, vertical GAA nanowire FETs were fabricated using a top-down approach. First, nanowires were defined by electron-beam lithography and subsequently etched anisotropically using reactive ion etching (RIE). The diameter of the nanowires was reduced by digital etching, consisting of repeated combined GeOx layer formation by plasma oxidation and removal in diluted HF solution. This way nanowires with a diameter down to 20 nm and a height of 210 nm were fabricated. A two-step process was employed for gate dielectric formation to ensure a low interface trap density: (i), deposition of a thin layer of Al2O3, followed by an O2-plasma post-oxidation step; (ii) deposition of a HfO2 dielectric layer to reach the required EOT (equivalent oxide thickness). TiN deposited by sputtering forms the gate metal. Planarization and isotropic dry etching were performed to remove the TiN on the top of the nanowire. After a second planarization step, NiGe-contacts were formed on the exposed top nanowire by Ni-deposition followed by a forming-gas annealing step. Finally, metal contacts for gate and source/drain were added.The resulting Ge-NW-pMOSFETs exhibit high electrical performances. A low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering (DIBL) of 35 mV/V and an I on/I off-ratio of 2.1×106 were measured for nanowires with a diameter of 20 nm. For 65 nm NWs, the I on/I off-ratio improves, which is attributed to the decreased contact resistance on top of the NWs, leading to larger on-currents. The peak transconductance for the Ge NWs reached ~190 µS/µm (V DS=-0.5 V). Adopting a GeSn/Ge-heterostructure, with GeSn on top of the nanowire used as source the device performances are strongly enhanced. The on-current I on was increased by ~32%, mostly due to the reduced contact resistivity of the smaller bandgap of GeSn compared to Ge. It was also observed that adopting GeSn alloys leads to an increase in transconductance, G max, to a respectable value of ~870 µS/µm, almost 3 times larger as reported to date for Ge NWs. Moreover, both SS and DIBL are improved by decreasing the NW diameter as a consequence of improved electrostatic gate control over the channel.These results demonstrate that the incorporation of GeSn into Ge-MOSFET technology yields a significant advantage and confirm its high potential for low-power-high-performance nanoelectronics.Fig. 1: (a) Schematic of the GAA nanowire FET based on a GeSn/Ge-heterostructure. (b) Optical image on the metallic contacts (c) Transfer curve of a Ge nanowire pFET with a diameter of 20 nm. The SS is 68 mV/dec and the DIBL is 35 mV/V. (d) Transfer curves of Ge0.92Sn0.08/Ge nanowire pFETs with a diameter of 65 nm and different EOTs. Acknowledgments The authors acknowledge support from the German BMBF project “SiGeSn NanoFETs”.

Vertical GeSn/Ge Heterostructure Gate-All-Around Nanowire p-MOSFETs

A process for the fabrication of vertical gate-all-around (GAA) nanowire p-FETs with diameters of down to 20 nm based on Ge and GeSn/Ge-heterostructures is presented. The resulting Ge-based devices exhibit a low subthreshold slope (SS) of 66 mV/dec, a low drain-induced barrier lowering of 35 mV/V and an I on/I off-ratio of 2.1×106 for devices with a diameter of 20 nm. Using a GeSn/Ge-heterostructure with GeSn as the top layer and source of the device, the on-current was increased by ~32%. With these results the high potential of incorporation of GeSn into Ge-MOSFET technology is demonstrated.

Study of Electrical Performance of Hetero-Dielectric Gate Tunnel Field Effect Transistor (HDG TFET): A Novel Structure for Future Nanotechnology

Although, dynamic power in portable mobile devices can be reduced by reducing power supply VDD on the cost of increased leakage current. Therefore, maintaining low leakage current in the device is serious issue for minimizing overall power consumption of the circuit and improving the battery life. The conventional Metal Oxide Field Effect Transistor (MOSFET) requires at least 60 mV of gate voltage for better current drive at room temperature which is difficult to achieve due to thermal limit. This limitation of gate voltage requirement degrades the performance of the device at lower VDD. Tunnel Field Effect Transistor (TFET) is a potential candidate to replace CMOS in deep-submicron region due to its lower subthreshold slope SS (< 60 mV/decade) at room temperature. Steep switching in TFET can extend the supply voltage scaling with improved energy efficiency for both digital and analog applications. Despite those advantages, TFETs are suffering from lower ON current and larger ambipolar current. To overcome these shortcomings, a new structure, known as Hetero-dielectric gate TFET (HDG TFET), has been proposed in the literature. Since, in the absence of the compact analytical model, it is difficult to understand the electrical behaviour of the HDG TFET device, therefore, the present paper presents an analytical model of transconductance parameter of HDG TFET device. The electrical performance analysis of HDG TFET device reflects that on current can be increased considerably by choosing gate material of higher work function near the source region which also suppresses the ambipolar current. It is also observed that a thinner silicon film and larger drain bias result in larger transconductance value.

Hysteresis-free and μs-switching of D/E-modes Ga2O3 hetero-junction FETs with the BV2/Ron,sp of 0.74/0.28 GW/cm2

In this Letter, we report on establishing high performance hysteresis-free and μs-switching depletion/enhancement-mode (D/E-mode) β-Ga2O3 heterojunction (HJ) field effect transistors (FETs) with the state-of-art power figure-of-merit (P-FOM). By optimizing the p-NiOx/n-Ga2O3 interface and n-Ga2O3 recess technology, a positive threshold voltage (VT) as well as a low subthreshold slope can be substantially achieved. The trade-off between the on-resistance (Ron,sp) and breakdown voltage (BV) is improved by incorporation of T-shaped NiOx, resulting in the Ron,sp of 6.24/13.75 mΩ cm2 and the breakdown voltage (BV) of 2145/1977 V for D/E-mode devices and yielding the P-FOM = BV2/Ron,sp to be 0.74/0.28 GW/cm2. To the best of all the authors' knowledge, those P-FOMs are the highest ones among all published lateral Ga2O3 FETs. Benefited from the high-quality interface, a negligible hysteresis of 4 mV and μs-switching can be essentially achieved, showing the great promise of Ga2O3 HJ-FETs for future high-power, high-efficiency, and high-speed power electronics.

Analog/RF Performance Analysis of a-ITZO Thin Film Transistor

This work reports RF and analog performance analysis of an amorphous Indium Tin Zinc Oxide thin film transistor. The various parameters affecting the performance of a-ITZO TFT like drain current, drain conductance, output resistance, transconductance, transconductance generation factor, early voltage, intrinsic gain, capacitances, cut off frequency, maximum frequency of oscillation, transconductance frequency product, gain frequency product, gain bandwidth product and gain transconductance frequency product have been closely examined. The device is further analyzed to investigate the impact of variation in physical parameters viz. dielectric material, dielectric thickness (𝐷𝑡) and temperature (T) on the RF/Analog performance. Use of high-k dielectric material in the simulated structure has resulted in low subthreshold slope (SS) of 0.62 V/decade, On voltage (𝑉𝑜𝑛) of - 0.29 V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 ratio of ~ 109, intrinsic gain (Av) of 104.5 dB and gain frequency product (GFP) of 1.86 GHz. The best results for dielectric thickness variation are obtained for Dt of 150 nm with SS of 0.22 V/decade, 𝑉𝑜𝑛 of -0.26 V, 𝐼𝑜𝑛/𝐼𝑜𝑓𝑓 of ~ 1010, Av of 175.69 dB and GFP of 2.39 GHz. In order to investigate device thermal reliability and stability, temperature analysis has also been done. To demonstrate the circuit level implementation of the simulated structure, a resistive load inverter circuit is simulated and analyzed for different variations (high-k, 𝐷𝑡 and T). It has also been concluded that TFT with high-k material or thinner dielectric at T=300 K provides best performance. This analysis confirms the potential of a-ITZO TFTs to realize high performance analog/RF circuits.

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV dec−1 subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with the attainment of an SS of 22 mV dec−1 at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Comprehensive review on electrical noise analysis of TFET structures

Tunnel Filed Effect Transistors (TFETs) have appeared as an alternative for conventional CMOS due to their advantages like very low leakage current and steep sub-threshold slope. In semiconductor devices, noise is considered an undesired signal that can deteriorate the desired signal. In TFET structures different noise sources affect the performance at different frequency ranges. This paper presents a comprehensive review of impact of electrical noise on the performance of various TFET structures. The impact of both low-frequency noise sources and high-frequency sources have been discussed thoroughly. The study of different types of electrical noises occur in simple TFET device and different structures of TFET is presented.

Analysis of modified P-I-N tunnel FET architecture for applications in low power domain

Tunnel FET with a few modifications is studied here for use in low power VLSI circuits as a worthy replacement of MOS based devices. The conventional TFET structure with P-I-N architecture is modified in the present work with dual gates, front and back, to give better control over the tunnelling current passing through the channel. In the proposed architecture asymmetrical lengths are utilised for the back and front gates, which improves the control even further. An SiGe based highly doped P + pocket is inserted in the intrinsic channel near the source end to rise the ON current and to increase the ION/IOFF ratio. In this device low subthreshold slope (SS) and lower DIBL values are also observed. The oxide layer below both the gates are engineered to optimise the combination of high and low k dielectric, lengths, to obtain performance improvement. Device Simulation Tool Silvaco Atlas is used to design and simulate the proposed device. Optimisation is done for the device with regards to length of channel, dimensions of the channel pocket, underlap and overlap lengths of the gates. The device is also tested over a wide range of temperatures to come to the best possible architecture, which is described here. The proposed device is proven to be a worthy contender to replace MOSFET in future ultra-low power, CMOS compatible VLSI circuits.

2D semiconductor SnP2S6 as a new dielectric material for 2D electronics

2D metal thiophosphate SnP2S6 was discovered as a new dielectric layer with a high dielectric constant (≈23), realizing a low subthreshold slope down to 69.4 mV dec−1 in the field effect transistor device geometry.

Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)

Abstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the performance of the conventional FET. In the proposed structure, the gate region is divided into three dielectric materials: TiO2/Al2O3/SiO2. This approach is chosen because high dielectric material alone near the source cannot improve the performance due to increase in fringing fields. This paper presents the detail processing of the proposed structure. We have evaluated and optimized the dc performance of the proposed N-DM_TGD TFET with the help of 2-D ATLAS simulator. The results were compared with those exhibited by dual metal hetero-gate-dielectric TFET, single metal hetero- gate-dielectric TFET and single metal triple-gate-dielectric TFET of identical dimensions. It has been observed that the DM_TGD device offers better transconductance (gm), lower subthreshold slope, lower ambipolar current and larger ON current.

Over 1.8 GW/cm2 beveled-mesa NiO/β-Ga2O3 heterojunction diode with 800 V/10 A nanosecond switching capability

In this Letter, we demonstrate a large-area (1-mm2) beveled-mesa p-NiO/β-Ga2O3 bipolar heterojunction diode (HJD) with a high Baliga's figure of merit of 1.84 (2.87) GW/cm2 from DC (pulsed) measurements. Benefiting from the suppression of electric field crowing at the designed mesa edge and bipolar current conductivity modulation, the resultant device exhibits advantageous characteristics, including a low subthreshold slope of 65 mV/decade, a low DC (pulsed) differential specific on-resistance of 2.26 (1.45) mΩ cm2, a high current density of 2 kA/cm2, and a high breakdown voltage of 2.04 kV. In particular, the Ga2O3 HJD exhibits an 800 V/10 A extreme switching capability with 16.4-ns reverse recovery characteristics, as well as high operation stability at a high temperature of 200 °C. This work, thus, makes a significant step toward reaching the promise of a high figure-of-merit in β-Ga2O3 power devices.

First demonstration of robust tri-gate β-Ga2O3 nano-membrane field-effect transistors

Nano-membrane tri-gate β-gallium oxide (β-Ga2O3) field-effect transistors (FETs) on SiO2/Si substrate fabricated via exfoliation have been demonstrated for the first time. By employing electron beam lithography, the minimum-sized features can be defined with the footprint channel width of 50 nm. For high-quality interface between β-Ga2O3 and gate dielectric, atomic layer-deposited 15 nm thick aluminum oxide (Al2O3) was utilized with tri-methyl-aluminum (TMA) self-cleaning surface treatment. The fabricated devices demonstrate extremely low subthreshold slope (SS) of 61 mV dec−1, high drain current (I DS) ON/OFF ratio of 1.5 × 109, and negligible transfer characteristic hysteresis. We also experimentally demonstrated robustness of these devices with current–voltage (I–V) characteristics measured at temperatures up to 400 °C.

Effect of Step Gate Work Function on InGaAs p-TFET for Low Power Switching Applications.

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.

Junctionless Silicon Nanotube Tunnel Field Effect Transistor Based Resistive Temperature Detector

A Junctionless Nanotube Tunnel Field Effect Transistor (JL-SiNT TFET) with platinum source and the aluminium gate electrode to enable band-to-band tunneling is proposed in this paper for significantly improved performance which is further used as an application of platinum resistive temperature detector according to earth’s environmental needs. The optimized device has been compared with the conventional Core-Shell Nanotube structure in view of analog parameters and electrical properties. High Ion/Ioff current ratio in the range of ~103, low subthreshold slopes, and high Ion current results in view of band-to-band tunneling induced in the device. Furthermore, we demonstrate that variations in the gate electrode work function, oxide thickness and silicon thickness can be used as design parameters to further upgrade the performance of the JL-SiNT TFET. The investigations showed that ON resistance of the sensor decreases in approximately by 2.3 times as the temperature increases from -200 °C to 200 °C. The resistance-temperature relationship shows high operability, high sensitivity, and the simulation is incongruent with the experimental results. The Nano Resistive temperature detector shows a sensitivity of −0.45%.

Rational design of hydrogen and nitrogen co-doped ZnO for high performance thin-film transistors

This work investigates the effect of nitrogen and hydrogen (N/H) co-doping on the performance of ZnO thin-film transistors (TFTs). Optimum N/H co-doped ZnO TFTs showed high field-effect mobility (25.5 cm2 Vs−1) and Ion/Ioff (107) and low sub-threshold slope (0.25 V/dec.) and threshold voltage (1.2 V). X-ray photo-electron spectroscopy (XPS) and low-frequency noise analysis suggest that the observed improved electrical performance may be attributed to the reduction of the defect concentration and the average interface trap density due to the occupation of the NO–H complex on the oxygen vacancy and Zn interstitials. Moreover, density functional theory calculation and XPS band structure results demonstrate that the N/H co-doped ZnO film slightly changed the valence band maximum energy offset, indicating that the N/H co-doping controlled the carrier concentration of the ZnO film due to the formation of neutral complex N–H states. The enhanced electrical performance of the N/H co-doped ZnO TFT shows significant potential for the use of low-cost thin film electronic applications.

Power-Speed Trade-Offs in Design of Scaled FET Circuits Using C/I DS Methodology

An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using C = C/IDS as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET) biased at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> . The proposed C-based methodology is used to study speed versus power trade-offs in both continuous-time (CT) and discrete-time (DT) circuits. Predictive Technology Models (PTMs) have been used to study performance of both MOSFET and FinFET (i.e. FET) devices in different technology nodes. This analysis shows that FinFET transistors exhibit a wider medium-inversion region compared to MOSFET devices, making them more convenient for high-speed and low-power designs. Additionally, this study proves that a lower sub-threshold slope factor results in an improved energy-efficiency of analog circuits.

An Ultra-low-power Static Random-Access Memory Cell Using Tunneling Field Effect Transistor

In this research article, an Ultra-low-power 1-bit SRAM cell is introduced using Tunneling Field Effect Transistor (TFET). This paper investigates feasible 6T SRAM configurations on improved N-type and P-type TFETs integrated on both InAs (Homojunction) and GaSb-InAs (Heterojunction) platforms. The voltage transfer characteristics and basic parameters of both Homo and Heterojunctions are examined and compared. The proposed TFET based SRAM enhances the stability in the hold, read, and write operations. This work evaluates the potential of TFET which can replace MOSFET due to the improved performance with low-power consumption, high speed, low sub-threshold slope, and supply voltage (VDD = 0.2 V). The results are correlated with CMOS 32nm technology. The proposed SRAM TFET cell is implemented using 30nm technology and simulated using an H-SPICE simulator with the help of Verilog-A models. The proposed SRAM TFET cell architecture achieves low power dissipation and attains high performance as compared to the CMOS and FINFET.

Investigation of threshold voltage shift and gate leakage mechanisms in normally off AlN/Al0.05Ga0.95N HEMTs on Si substrate

In this study, normally off AlN/Al0.05Ga0.95N high-electron-mobility transistors (HEMTs) on a Si substrate were fabricated by adjusting the surface states of the heterostructure. The device exhibited an extremely low reverse gate leakage current of 10−7 mA/mm due to the high Schottky-barrier height for Ni/Au on AlN/Al0.05Ga0.95N. A high ION/IOFF of 108 and a low subthreshold slope of 63 mV/decade were attained for this device. Moreover, breakdown voltages of 665 V and 1000 V were reached in these devices, with a gate-to-drain distance of 26 µm, for a grounded substrate and a floating substrate, respectively. In order to evaluate the reliability of the device, bias-induced and temperature-induced threshold-voltage-instabilities were investigated. The threshold voltage of the device shifted with gate bias stress due to electrons in the channel trapped by bulk traps. Thermally activated electrons releasing from traps decreased the threshold voltage with increasing measurement temperature. This indicates that the reliability in the threshold-voltage stability for the normally off device is dominated by the deep traps in epitaxially grown AlN/Al0.05Ga0.95N. Finally, the gate leakage mechanisms in AlN/Al0.05Ga0.95N HEMTs were investigated. The reverse and forward gate leakage was dominated by Poole–Frenkel tunneling and thermionic emission, respectively.

(Invited) Highly Stable Self-Aligned Top-Gate Indium Gallium Zinc Oxide Thin-Film Transistors for High-Resolution OLED TV and Mobile Displays

Indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted much attention because of their high electron mobility values (> 10 cm2/Vs) and because they can be processed at low temperature to produce large-area displays with the potential of low production costs. The IGZO TFTs require smaller RC signal delay with shorter channel length for high-resolution display applications. Therefore, it’s necessary to use self-aligned top-gate (TG) oxide TFT structure with smaller channel length for high-resolution, high-speed, low-power, and narrow-bezel displays. The IGZO TFTs also need good electrical stability under positive/negative bias temperature stress (P/NBTS) with decent TFT properties for peripheral gate driver integrated large size organic light emitting diode (OLED) TVs. TG IGZO TFTs for display applications such as OLED TVs typically use longer channel length (> 4 µm) due to negative threshold voltage (Vth) shift and Vth non-uniformity issues with smaller channel length, which is mainly caused by hydrogen diffusion near source/drain regimes during device integration. We fabricated TG IGZO TFTs by using Applied Material’s CVD/PVD tools to achieve excellent electrical stability and Vth uniformity by balancing oxygen and hydrogen diffusion into oxide channel layer such as IGZO. Suppressing carrier densities at the interface between gate insulator (GI) and IGZO by increasing oxygen diffusion with IGZO pre-annealing in air and TFT post anneal in air, and by minimizing vacuum annealing impact during GI deposition makes the IGZO TFTs more resistive with more positive Vth shift. On the other hands, more hydrogen diffusion into IGZO from GI, ILD, and passivation layers during device integration or TFT post annealing makes the IGZO TFTs more conductive with more negative Vth shift and worse Vth uniformity, but it helps to improve electrical stability with smaller Vth shift under PBTS by passivating defects inside IGZO. Therefore, there is trade-off between Vth uniformity and electrical stability due to the dominance of the diffusion between oxygen and hydrogen. By balancing the diffusion of oxygen and hydrogen, the IGZO TFTs can minimize negative Vth shift even with shorter channel for high-resolution display applications and achieve good electrical stability for pixel and peripheral gate driver circuits integrated in display panel. We successfully demonstrated excellent electrical properties such as high mobility (µFE), low sub-threshold slope (SS), good threshold voltage (Vth) position, and low off-leakage current from TG IGZO TFTs. The positions of Vth can be optimized by controlling carrier densities at the interface between GI and IGZO during device integration even with different GI temperature and power (Fig. 1). Here, GI type A is deposited at a low temperature of 225 ºC with a high RF power of 2400 W. GI type B is deposited at a high temperature of 270 ºC with a high RF power of 2400 W. GI type C is deposited at a high temperature of 270 ºC with a low RF power of 1600 W. In order to investigate the channel length dependency of Vth, Vth values were extracted from transfer characteristics at VDS = +1 V with various TFTs by fixing channel width of 12 µm and varying the channel length from 10 µm down to 3 µm. The differences between maximum Vth and minimum Vth, Vth (Max–Min), from GI type A, B, and C are 0.35 V, 0.48 V, and 1.20 V, respectively. Total resistance in TFTs was extracted from the measured IDS values by varying VGS from 12 V to 20 V with channel length from 10 µm down to 5 µm by transmission line method. Extracted 2∆L, the difference between mask channel length and effective channel length, from GI type A, B, and C are 0.78 µm, 0.87 µm, and 1.05 µm, respectively. The IGZO TFTs with higher GI power show better TFT uniformity than lower power GI without notable negative Vth shift and non-uniformity even with shorter channel length from 10 µm down to 3 µm by minimizing hydrogen diffusion into IGZO (Fig. 2). The IGZO TFTs with lower GI power show better stability under PBTS due to more hydrogen diffusion into IGZO. On the other hands, the IGZO TFTs show better stability under both PBTS and NBTS with higher GI temperature than lower temperature GI due to more hydrogen diffusion into IGZO (Fig. 3). Therefore, high power/high temperature GI is preferred for high-resolution mobile/VR displays considering short channel length effect and low power/high temperature GI is preferred for gate driver integrated OLED TVs considering stability, especially PBTS. Figure 1