Low Reference Spur Research Articles

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur

Analysis and Design of a Sub-Sampling PLL of Low Phase Noise and Low Reference Spur

A fast-locking low-reference spur cascaded PLL with gate-diffusion input-based phase detector and pulse width amplifier

ABSTRACT This paper presents a newly proposed high-order cascaded phase-locked loop using a type-I phase-locked loop in the second stage. The type-I phase-locked loop includes a gate-diffusion-input-based phase detector and pulse width amplifier that leads to breaking the trade-off between reference spur and locking time. Moreover, a type-I phase-locked loop deploys a pulse width amplifier after a gate-diffusion-input-based phase detector with variable gain to amplify the phase error between the reference clock and the output of the voltage-controlled oscillator. The proposed architecture has been implemented in a 180-nm semiconductor laboratory CMOS technology. The proposed fifth-order cascaded phase-locked loop achieves the reference spur of −77 dBc, while the conventional first-stage charge-pump-based phase-locked loop achieves −59.7 dBc. It measures the 1.2 s settling time, whereas conventional first stage charge-pump-based phase-locked loop measures 2.4 s settling time. The cascaded phase-locked loop operates at 2.4 GHz output frequency, and the simulated phase noise at 1 MHz offset frequency is −105.4 dBc/Hz. It consumes 5.8 mW from a 1.8 V power supply.

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter

A low-power low-jitter phase-locked loop (PLL) with phase noise improvement for radio frequency transceivers is presented in this paper. The in-band phase noise and out-of-band phase noise are both reduced due to the time-amplifying technique and the class-C voltage-controlled oscillator (VCO), respectively. In addition, a low current mismatch charge pump (CP) is used here to guarantee a low reference spur. The proposed PLL is fabricated in a 65-nm CMOS mixed-signal process with an area of 0.220 mm2, and the reference clock is 150 MHz. The measurement results show that this PLL operates at 1-V supply voltages and achieves 8.5–10.3-GHz tuning range, 407.807-fs integrated jitter at 9.6 GHz, 7.20-mW total power consumption, resulting in a −239.22-dB figure-of-merit (FoM). The measured reference spur is −51.27 dBc at a 150-MHz offset frequency.

A Wideband and Low Reference Spur PLL with Clock Feedthrough Suppressed and Low Current Mismatch Charge Pump and Symmetrical CML Divider

This paper presents the design and performance analysis of a wideband charge-pump phase-locked loop (CPPLL) characterized by low reference spur and low phase noise. The proposed CPPLL, operating as a wideband phase-locked loop (PLL) with a reference frequency of 100 MHz, achieves a wide tuning range of 40% from 2.0 GHz to 3.0 GHz. A clock feedthrough suppressed charge pump with additional bias current branches is used to reduce the PLL’s loop reference spur. The 4-stage current mode logic (CML) divide-by-2/3 circuit is utilized in the frequency divider to achieve high-speed frequency division. The circuit of an AND gate and latch in the 2/3 divider adopts a full differential symmetric structure to minimize the phase error of high-frequency differential signals. The voltage-controlled oscillator (VCO) is designed to provide a wide tuning range while optimizing the trade-off between the phase noise and power consumption. The fabricated PLL is implemented using a 0.13 µm CMOS process. Experimental measurements reveal a reference spur of −74.39 dBc at an oscillation frequency of 2.4 GHz. Moreover, the CPPLL achieves phase noise of −102.55 dBc/Hz@100 kHz and −127.15 dBc/Hz@1 MHz, while consuming 33.6 mW under a 1.2 V supply voltage. The integrated root-mean-square (rms) jitter, measured from 10 kHz to 10 MHz, is 340.99 fs, and the figure-of-merit (FoM) is −234.08 dB at a carrier frequency of 2.4 GHz, highlighting the potential of the proposed PLL for integrated circuit applications.

A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

In this article, a dual-loop dual-output frequency synthesizer designed for IEEE802.11aj (45 GHz) standard is presented. In order to support the super-heterodyne transceiver, the Loop1 output frequency is fixed for easy design of high-performance IF transceiver and filter, and the Loop2 output frequency varies for the channel selection according to the IEEE802.11aj (45 GHz) standard. The power hungry high-speed prescaler (or multi-modulus-divider) is replaced with a mixer in Loop2, thus the in-band phase noise and DC power consumption can be improved. The dual-loop dual-output synthesizer is fabricated in 0.13 µm SiGe BiCMOS technology, occupies an area of 2.7 mm × 2.4 mm, and consumes 610 mW DC power. Measured results show the phase noise of the frequency synthesizer are −79.3 dBc/Hz@10 kHz and −129.1 dBc/Hz@10 MHz at 12.96 GHz for Output1 and −76.6 dBc/Hz@10 kHz and −117.2 dBc/Hz@10 MHz at 32.535 GHz for Output2. The low-reference spur of −69.2 dBc and low-power level spurious tones at the outputs are observed during the measurement. To the best of our knowledge, this work is the first reported dual-loop dual-output synthesizer designed for IEEE802.11aj (45 GHz) standard.

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Design of integer‐ N PLL frequency synthesiser for E‐band frequency for high phase noise performance in 5G communication systems

A phase-locked loop (PLL) frequency synthesiser is designed for 5G E-band frequency. ADF4155-PLL chip with an external (loop filter, prescaler, VCO and an external reference oscillator) is simulated using the ADIsimPLL tool. With a third-order passive filter having 1 MHz loop bandwidth and 45° phase margin, simulation results show that the proposed synthesiser achieves a total phase noise (PN) of -81.50 and -115.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for (71-76 GHz) and -80.39 and -114.7 dBc/Hz at 100 kHz and 10 MHz, respectively, for the highest (81-86 GHz) 5G frequency range even if -160 dBc/Hz VCO noise floor and -170dBc/Hz reference PN floor are integrated in the design. Also, the performance of the system in terms of RMS jitter and reference spurs are verified. The proposed synthesiser for 5G application presents very low reference spurs (-113, -112 dBc) at 50 MHz offset frequency and low RMS jitter (0.39, 0.40 ps) for 70 and 80 GHz frequency band, respectively.

A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TDC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and -75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power consumption was 6.0 mW.

A low reference spur phase-locked loop realized with dynamic current injection charge pump

A low reference spur phase-locked loop realized with dynamic current injection charge pump

A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios

An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1–10.6-GHz band efficiently for high data-rate short-range wireless connectivity even in overcrowdedness of the frequency spectrum. Frequency synthesizers tailored to the UWB-based CR should provide wide lock range, multiple frequency bands, and low in-band spurs while consuming low power. This paper investigates a low power, wide lock range, integer-N frequency synthesizer approach with 132-MHz frequency step and 57 subbands in the UWB band. Two-stage supply regulated differential ring oscillator provides linear and wide tuning range with voltage controlled oscillator gain of 22.5 GHz/V and low supply-noise sensitivity. A modular true-single-phase-clock programmable divider achieves wide operating frequency range of 0.1–6.5 GHz and power efficiency of 6.25 GHz/mW by compensating leakage current at the dynamic nodes with conditional latches. Replica-based digital calibration reduces the current mismatch of the charge pump to <1% for low in-band reference spurs of <−60 dBc. A frequency synthesizer test chip was fabricated in 65-nm complementary metal–oxide–semiconductor technology. The active area of the frequency synthesizer is 0.12 mm2. It achieves <−30-dBc integrated phase noise and enables the UWB-based CR to get bit error rate of <10−3 while consuming <−10.1 mW.

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability of suppressing jitter of a VCO, we propose a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier. By the proposed FPEC technique, accumulated jitter of a VCO can be removed intensively in a short interval, thereby suppressing jitter dramatically. Based on a PLL topology having an intrinsic integrator in a VCO, the proposed architecture can also achieve a low reference spur despite a high multiplication factor (i.e., 64). This paper also presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur. The proposed PLL was fabricated in a 65-nm CMOS process. The measured rms jitter integrated from 1 kHz to 80 MHz and the reference spur of the output signal with a 3.008-GHz frequency were 357 fs and −71 dBc, respectively. The total active area was 0.047 mm2, and the power consumption was 4.6 mW.

A Low-Reference Spur MDLL-Based Clock Multiplier and Derivation of Discrete-Time Noise Transfer Function for Phase Noise Analysis

A multiplying delay-locked loop (MDLL)-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a phase-locked loop mode to align the coarse phase and an MDLL mode to obtain a delay-lock. With non-overlap dual phase detector pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line from that of delay line. The NTF includes aliasing effect and shows better accuracy than the prior voltage controlled oscillator realignment-based approaches. This clock multiplier occupies an active area of 0.047-mm2 in 40-nm CMOS process. The clock multiplication ratio ( $N$ ) is an integer value from 8 to 27. With a low-cost 19.2-MHz TCXO reference, 153.6–518.4 MHz clocks were successfully generated, and a phase noise of −124 dBc/Hz at 100-kHz offset from a 518.4-MHz clock, rms jitter of 1.28 ps, and −65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 and 1.1 V supplies.

A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

This paper presents a novel high performance, ultra-low power scalable CMOS charge pump (CP) design for analog phase-locked loops (PLLs) fabricated in all-digital nanoscale IC processes. The compact CP circuit uses four minimally-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator frequency in the PLL control loop. Unlike the state of the art designs, the proposed CP topology does not use current mirrors, nor does it suffer from traditional mismatch errors due to its unique structure. Additionally, this charge transfer-based CP has the ability to operate at very low supply voltages well below 1 V. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop-based phase-frequency detector resulting in a reduced PLL control loop delay and very low reference spurs in the overall PLL design. The proposed CP has been placed in a 0.5---10 GHz PLL, fabricated, and physically tested in an all-digital 40 nm TSMC CMOS process. Additionally, post-silicon measurements of the CP circuit have been completed with a variable 0.2---1.2 V supply and a 50 MHz---1 GHz reference frequency. The proposed CP has an active area of 0.0004 mm2, consumes on average 250 pW power, and has a 0.1°---0.3° phase error, dependent on the PLL frequency of operation.

A wideband low‐spur 0.18‐µm CMOS phase‐locked loop with bandwidth calibration

SummaryThis paper presents a 0.18‐µm complementary metal‐oxide‐semiconductor wideband phase‐locked loop with low reference spurs. The dual‐level charge‐pump current calibration technique is proposed to maintain a constant loop bandwidth for wide operation frequency range and achieve low reference spurs. The first level charge‐pump current calibration is seamlessly incorporated in the automatic frequency band hopping control and the mechanism also ensures enough negative transconductance for the voltage‐controlled oscillator to function throughout the whole frequency range. The charge‐pump current mismatch is calibrated by the second level charge‐pump current calibration combined with the pulse‐width scaling technique. The operation frequency range of the phase‐locked loop covers from 4.7 GHz to 6.1 GHz. The measured phase noise is−116 dBc/Hz at 1‐MHz offset and the reference spurs are below−66.8 dBc. Copyright © 2015 John Wiley &amp; Sons, Ltd.

A Dividerless PLL With Low Power and Low Reference Spur by Aperture-Phase Detector and Phase-to-Analog Converter

A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise is introduced in this paper. A new phase detection mechanism using aperture-phase detector (APD) and phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error between reference and VCO, and then controls the current amplitude of the following charge pump (CP). The charging and discharging currents in the proposed CP have equal pulse width and equal small amplitude in locked state, which reduces the reference spur and power consumption of the CP effectively. Moreover, compared to the conventional CP with the same bias current in locked state, the proposed CP can contribute a much lower noise to the PLL output. In addition, a method of tunable loop gain with theoretical analysis is introduced to reduce the PLL output jitter. The proposed PLL is fabricated in a standard 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu$</tex></formula> m CMOS process. It consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\,\times\,$</tex> </formula> 0.86 mm. The reference spur of the proposed PLL is measured to be <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}80$</tex></formula> dBc/ <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}74$</tex></formula> dBc and an in-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}103$</tex> </formula> dBc/Hz at 100 kHz offset is achieved.

A low reference spur quadrature phase-locked loop for UWB systems

This paper presents a low phase noise and low reference spur quadrature phase-locked loop (QPLL) circuit that is implemented as a part of a frequency synthesizer for China UWB standard systems. A glitch-suppressed charge pump (CP) is employed for reference spur reduction. By forcing the phase frequency detector and CP to operate in a linear region of its transfer function, the linearity of the QPLL is further improved. With the proposed series-quadrature voltage-controlled oscillator, the phase accuracy of the QPLL is guaranteed. The circuit is fabricated in the TSMC 0.13 μm CMOS process and operated at 1.2-V supply voltage. The QPLL measures a phase noise of −95 dBc/Hz at 100-kHz offset and a reference spur of −71 dBc. The fully-integrated QPLL dissipates a current of 13 mA.

A High-Performance PLL With a Low-Power Active Switched-Capacitor Loop Filter

A 2.5-GHz phase-locked loop (PLL) employing a low-power active switched-capacitor loop filter is presented. A subthreshold inverter-based active loop filter is presented and analyzed. Advantages such as type-II loop dynamics, low reference spurs, and small on-chip capacitors are achieved. In addition, 1/f noise of the inverter amplifier can be suppressed by the filter's auto-zeroing operation. The prototype is designed and fabricated in a 0.18- μm CMOS technology. Measurement results show phase noise of -86 dBc/Hz at a 100-kHz offset, -124.0 dBc/Hz at a 3-MHz offset, and a reference spur level of -64 dBc. The PLL consumes about 16 mW with 0.46 mW dedicated to the loop filter active components.

A fractional-N PLL with small ΔK vco wideband LC-VCO and current-matching CP for M-DTV systems

An Σ-Δ fractional-N frequency synthesiser with small K vco-variation wideband LC voltage controlled oscillator (LC–VCO) and current-matching charge pump (CP) for Mobile Digital television Systems is presented. To achieve small VCO-gain (K vco) variation, a parallel switched varactor array is proposed to the conventional wideband LC-VCO with switched capacitor array, the value of the switched varactor is pre-set and both arrays are controlled by the same switching code. Perfect current matching and good stability are obtained by the improved CP with an added bias branch circuit for low reference spur. The chip was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.25 µm complementary metal-oxide-semiconductor process and draws 12 mA from a 2.5 V supply voltage. The synthesiser covers a wide tuning range from 0.82 to 1.85 GHz with two integrated LC-VCOs, and each VCO achieves a K vco variation of less than 16% with a tuning range of more than 46%. The current mismatch of CP is as low as 1.2%. The measured close-in and out-of-band phase noise are −83.5 dBc/Hz@10 kHz and −127 dBc/Hz@1 MHz, respectively, the reference spur is −76.3 dBc.

The Design of a K-Band 0.8-V 9.2-mW Phase-Locked Loop

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98dBc/Hz. The locking range of the PLL is from 22.6GHz to 23.3GHz and the reference spur level is -69dBm that is 54dB bellow the carrier. The power consumption is 9.2mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.