A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios

Abstract

An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1–10.6-GHz band efficiently for high data-rate short-range wireless connectivity even in overcrowdedness of the frequency spectrum. Frequency synthesizers tailored to the UWB-based CR should provide wide lock range, multiple frequency bands, and low in-band spurs while consuming low power. This paper investigates a low power, wide lock range, integer-N frequency synthesizer approach with 132-MHz frequency step and 57 subbands in the UWB band. Two-stage supply regulated differential ring oscillator provides linear and wide tuning range with voltage controlled oscillator gain of 22.5 GHz/V and low supply-noise sensitivity. A modular true-single-phase-clock programmable divider achieves wide operating frequency range of 0.1–6.5 GHz and power efficiency of 6.25 GHz/mW by compensating leakage current at the dynamic nodes with conditional latches. Replica-based digital calibration reduces the current mismatch of the charge pump to <1% for low in-band reference spurs of <−60 dBc. A frequency synthesizer test chip was fabricated in 65-nm complementary metal–oxide–semiconductor technology. The active area of the frequency synthesizer is 0.12 mm2. It achieves <−30-dBc integrated phase noise and enables the UWB-based CR to get bit error rate of <10−3 while consuming <−10.1 mW.