Low Reference Spur Research Articles

Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump

A clock multiplier combines the low reference spur of a PLL with the low phase noise of a recirculating DLL. It uses a ring oscillator that has two pulses running simultaneously that are phase independent. One pulse is used by a PLL to precisely set ring delay while the other pulse is periodically realigned with the reference phase by a process of pulse removal and reinsertion, similar to a DLL. The DLL reference spur due to static phase offset is eliminated, since the realigned pulse is not used to control the delay. A self-correcting charge pump is introduced that corrects for mismatches in the actual up-and down currents. The 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 90 nm CMOS circuit has -122 dBc/Hz phase noise @ 200 kHz offset of an 800 MHz carrier, - 48 dBc reference spur and consumes 15 mW from a 1 V supply.

Notice of Violation of IEEE Publication Principles: A low reference spurs 1-5 GHz 0.13 μm CMOS frequency synthesizer using a fully-sampled feed-forward loop filter architecture

Notice of Violation of IEEE Publication Principles<br><br>"A Low Reference Spurs 15 GHz 0.13 μm CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop Filter Architecture"<br>by Maxim, A.<br>in the IEEE Journal of Solid-State Circuits,<br>Volume 42, Issue 11, Nov. 2007 Page(s):2503 - 2514<br><br>After careful and considered review, it has been determined that the above paper is in violation of IEEE's Publication Principles.<br><br>Specifically, the paper contains information that Adrian Maxim admits had been falsified. In response to an inquiry on this misconduct, Mr. Maxim acknowledged that the following people who have been listed as co-authors on several of his papers are fabricated names and that he is the only author:<br><br>C. Turinici, D. Smith, S. Dupue<br><br>Additionally, in papers by Mr. Maxim that have co-authors other than those listed above, it was discovered in some cases that he had not consulted with them while writing the papers, and submitted papers without their knowledge.<br><br>Although Mr. Maxim maintains that not all of the data is falsified, IEEE nevertheless cannot assure the integrity of papers posted by him because of his repeated false statements.<br><br>Due to the nature of this violation, reasonable effort should be made to remove all past references to the above paper, and to refrain from any future references. <br/> A wide tuning range, low phase noise and spurs, multi-gigahertz frequency synthesizer was realized in 0.13 μm CMOS using a fully-sampled feed-forward loop filter. Both the integral and proportional loop filter paths use sample and hold switched-capacitor networks that completely isolate the oscillator from the charge-pump switching transients. The sampled nature of the filter, together with a digital domain implementation of the ripple-filtering pole spread the impulsive energy coming from the charge-pump current injection over several reference clock cycles, resulting in a dramatic reduction of the oscillator control signal ripple and thus a very low reference spur level. A multi-regulator PLL architecture reduces the supply injected noise and spurious tones, allowing the integration of the synthesizer on the same die with a large digital core, as required by modern single-chip receiver SoCs. PLL specifications include: < 1deg rms double-sided integrated phase noise from 1 kHz to 10 MHz, -85 dBc reference spurs, < -80 dBc supply injected spurs, 300 times 750 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area and < 100 mW power dissipation from a single 2.5 V supply.

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-/spl mu/m CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 /spl mu/s.