Low-power Techniques Research Articles

An Adaptive and Integrated Low-Power Framework for Multicore Mobile Computing

Employing multicore in mobile computing such as smartphone and IoT (Internet of Things) device is a double-edged sword. It provides ample computing capabilities required in recent intelligent mobile services including voice recognition, image processing, big data analysis, and deep learning. However, it requires a great deal of power consumption, which causes creating a thermal hot spot and putting pressure on the energy resource in a mobile device. In this paper, we propose a novel framework that integrates two well-known low-power techniques, DPM (Dynamic Power Management) and DVFS (Dynamic Voltage and Frequency Scaling) for energy efficiency in multicore mobile systems. The key feature of the proposed framework is adaptability. By monitoring the online resource usage such as CPU utilization and power consumption, the framework can orchestrate diverse DPM and DVFS policies according to workload characteristics. Real implementation based experiments using three mobile devices have shown that it can reduce the power consumption ranging from 22% to 79%, while affecting negligibly the performance of workloads.

Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design

Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.

Function and behaviour: use-wear evidence from Upper Paleolithic tools in southern Shanxi Province, North China

Lithic use-wear analysis has become a principal approach for interpreting the function of stone tools and inferring human behaviour. This study presents the results of use-wear analysis on lithic tools excavated from the Upper Paleolithic sites of Xiachuan and Chaisi in the southern part of Shanxi Province, North China. In this study, microblades and so-called core-like tools from these two sites were selected for examination by low-power techniques to identify their use patterns. The results suggest that approx. 30% of microblades might have been used mainly to process animal substances, and a lower percentage for vegetal substances. Based on the use-wear evidence, items classified as core-like tools should be regarded as microblade-cores, since they exhibit few traces of utilisation.

A 69-dB SNR 89-μW AGC for Multifrequency Signal Processing Based on Peak-Statistical Algorithm and Judgment Logic

A novel peak-statistical algorithm and judgment logic (PSJ) for multifrequency signal application of Autogain Control Loop (AGC) in hearing aid SoC is proposed in this paper. Under a condition of multifrequency signal, it tracks the amplitude change and makes statistical data of them. Finally, the judgment is decided and the circuit gain is controlled precisely. The AGC circuit is implemented with 0.13 μm 1P8M CMOS mixed-signal technology. Meanwhile, the low-power circuit topology and noise-optimizing technique are adopted to improve the signal-to-noise ratio (SNR) of our circuit. Under 1 V voltage supply, the peak SNR achieves 69.2 dB and total harmonic distortion (THD) is 65.3 dB with 89 μW power consumption.

A Digital-Based Low-Power Fully Differential Comparator

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence[Formula: see text] Virtuoso Analog Design Environment using UMC 180[Formula: see text]nm CMOS technology at 1.8[Formula: see text]V supply.

Application-Specific Low-Power Multipliers

In this paper we propose techniques for decreasing the power consumption of multipliers. The proposed techniques exploit data statistics. Specifically we propose two architectures for two-input signed multipliers, namely selective activation multiplier and partitioned multiplier. To illustrate the benefits achieved by the proposed architectures, their application in the implementation of multipliers used in DCT and DWT is detailed. The power reduction reported is up to $20.7$ percent for cases of practical interest. The proposed multipliers can be easily implemented, adapted, and combined with prior-art low-power techniques with a moderate area and time overhead.

Low-power low-area techniques for multichannel recording circuits dedicated to biomedical experiments

Abstract This paper presents techniques introduced to minimize both power and silicon area of the multichannel integrated recording circuits dedicated to biomedical experiments. The proposed methods were employed in multichannel integrated circuit fabricated in CMOS 180nm process and were validated with the use of a wide range of measurements. The results show that both a single recording channel and correction blocks occupy about 0.061 mm2 of the area and consume only 8.5 μW of power. The input referred noise is equal to 4.6 μVRMS. With the use of additional digital circuitry, each of the recording channels may be independently configured. The lower cut-off frequency may be set within the range of 0.1 Hz–700 Hz, while the upper cut-off frequency, depending on the recording mode chosen, can be set either to 3 kHz/13 kHz or may be tuned in the 2 Hz–400 Hz range. The described methods were introduced in the 64-channel integrated circuit. The key aspect of the proposed design is the fact that proposed techniques do not limit functionality of the system and do not deteriorate its overall parameters.

Polymerization of acrylic acid using atmospheric pressure DBD plasma jet

In this paper polymerization of acrylic acid was performed using non thermal atmospheric pressure plasma jet technology. The goal of this study is to deposit organic functional coatings for biomedical applications using a low cost and rapid growth rate plasma jet technique. The monomer solution of acrylic acid was vaporized and then fed into the argon plasma for coating. The discharge was powered using a laboratory made power supply operating with sinusoidal voltage signals at a frequency of 10 kHz. The optical emission spectra were collected in order to get insight into the plasma chemistry during deposition process. The coatings were characterized using Fourier transform infrared spectroscopy, atomic force microscopy and growth rates analysis. A high retention of carboxylic functional groups of the monomer was observed at the surface deposited using this low power technique.

Design of Low Power and Area Efficient Full Adder using Modified Gate Diffusion Input

The low power techniques are becoming more important due to rapid development of portable digital applications; demand for high-speed and low power consumption.GDI (Gate Diffusion Input) is one of the low power and area efficient technique. GDI requires less number of transistors compared to CMOS technology. The basic cell of GDI consists of two transistors where three terminals i.e Gate, Source and Drain considered as inputs. Therefore, it is helpful for low power, delay and area. But the disadvantage of GDI is its output has poor logic swing .This paper presents low power high performance multiplexer based full adder design in CADENCE VIRTUOSO GPDK 45nm Technology. The power consumption comparison is also made based on CMOS and GDI design technique.

DHL‐cache: dynamic per history length adjustment for low‐power L2 cache

The significant power dissipation of the on-chip L2 cache is a major concern in modern microprocessors. This Letter proposes a unique low-power technique for a high-associative large L2 cache that has fragmented locality by L1 cache. The dynamic per history length adjustment cache (DHL-cache) dynamically selects the qualified way candidates to be accessed and controls the way-prediction window size based on the access history pattern. With a high degree of the way-prediction accuracy, the DHL-cache shows a 55.3% energy-delay product improvement over the location-cache with minimum hardware support. Therefore, the DHL-cache alleviates the power limit issue for L2 cache, even with high associativity and fragmented locality.

Design of Current Mode MTCMOS Sense Amplifier with Low Power and High Speed

This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.

Hafting wear on quartzite tools: An experimental case from the Wulanmulun Site, Inner Mongolia of north China

Abstract Usewear analysis is one of the most important and significant methods in studying the hafting wear. The raw material used in this article is quartzite gathered from identified raw material resource of Wulanmulun Site, and the wooden handle and hemp rope are used as the binding material of accomplishing the experimental study on the hafting wear on quartzite tools. The low-power technique was applied in observing stone specimens. The research shows that the hafting wear on quartzite tools has its own regular pattern that can be well recognized by the low-power technique. Generally, the difference of major features and patterns of hafting wear occurred and distributed at areas of the lateral edges, surface ridges and basal edges of the lower part on the specimens can be well distinguished. The binding material, binding method, processing way of binding and the morphology of stone specimen themselves can be also affected factors to the hafting wear patterns. The present study may contribute a partial set of reference standards in constructing hafting wear patterns on the quartzite tools and aid interpretation of features observed on archaeological assemblages on the basis of the low-power technique.

RF Power Gating: A Low-Power Technique for Adaptive Radios

In this paper, we propose a low-power technique, called RF power gating, which consists in varying the active time ratio (ATR) of the RF front end at a symbol time scale. This technique is especially well suited to adapt the power consumption of the receiver to the performance needs without changing its architecture. The effect of this technique on the bit error rate (BER) performances is studied for a basic estimator in the specific case of minimum-shift keying signaling. A system-level energy model is also derived and discussed to estimate precisely the power reduction based on the characteristics and the power consumption of each block. This model allows highlighting the different contributors of the power reduction. The BER results and the energy model are finally merged to determine the best ATR meeting the design constraints. Applying this technique to the IEEE 802.15.4 standard, this paper shows that an ATR of 20% is a good tradeoff to meet the packet error rate constraint while maximizing the energy reduction ratio. Using typical block power consumptions, an energy reduction ratio around 20% can be reached. Even better energy reduction ratios ( $\sim 60$ %) are also achievable when most of the blocks are power-gated.

Low‐power technique for dynamic comparators

A low-power technique to reduce the power consumption of the dynamic comparators is presented. Using this technique, the pre-amplification phase of the comparator is stopped without any effect on the dynamic behaviour of the comparator. Therefore, the power consumption of the pre-amplifier stage which is the main part of the total power consumption is reduced significantly. Simulation results in various comparators reveal that the proposed technique reduces the total power consumption by more than 50%.

A Power Saving Set Associative Cache Model

Background/Objectives: Placing conflict cache lines in alternate set is proposed for set associative caches in literature. The conflicting lines are placed in one alternate set for each set. Methods/Statistical Analysis: This paper proposes architecture to place conflicting lines in set with maximum vacant ways in set associative caches. The model introduces one register per cache way with number of bits equal to number of cache sets. A sequential circuit using the register enables the cache ways of any set. The unoccupied ways are disabled. The proposed model is simulated with SPEC2K benchmarks. The power consumption is calculated using Quartus 2 tool and verilog code. Findings: An average improvement in power consumption of 68% for benchmarks with partial filled cache ways is observed with average memory access degradation of about 4.86%. A performance degradation in average memory access time of about 34% compared with direct mapped cache system and 3% compared with random placement algorithm is observed for the proposed system. The proposed model is for power consumption as is validated from the findings. The proposed model can be adapted for set associative caches to improve power consumption. Applications/Improvements: A model with optimal operational cache sets with methods to decrease power dissipation of sequential circuits, low power techniques for digital circuits can be used to improve the power consumption

Design and experimental demonstration of low-power CMOS magnetic cell manipulation platform using charge recycling technique

We present the world’s first charge-recycling-based low-power technique of complementary metal–oxide–semiconductor (CMOS) magnetic cell manipulation. CMOS magnetic cell manipulation associated with magnetic beads is a promissing tool for on-chip biomedical-analysis applications such as drug screening because CMOS can integrate control electronics and electro-chemical sensors. However, the conventional CMOS cell manipulation requires considerable power consumption. In this work, by concatenating multiple unit circuits and recycling electric charge among them, power consumption is reduced by a factor of the number of the concatenated unit circuits (1/N). For verifying the effectiveness, test chip was fabricated in a 0.6-µm CMOS. The chip successfully manipulates magnetic microbeads with achieving 49% power reduction (from 51 to 26.2 mW). Even considering the additional serial resistance of the concatenated inductors, nearly theoretical power reduction effect can be confirmed.

모바일 OLED 디스플레이를 위한 인간 시각 만족의 최적 전력 절감 색 변환

Due to the merits of OLED displays such as fast responsiveness, wide view angle, and power efficiency, their use has increased. However, despite the power efficiency of OLED displays, the portion of their power consumption among the total power consumption is still high since user interaction-based applications such as instant messaging, video play, and games are frequently used. Their power consumption varies significantly depending on the display contents and thus color transformation is one of the low-power techniques used in OLED displays. Prior low-power color transformation techniques have not been rigorously studied in terms of satisfaction of the human visual system, and have not considered optimal visual satisfaction and power consumption at the same time in relation to color transformation. In this paper, we propose a novel low-power color transformation technique which strictly considers human visual system-awareness as well as optimization of both visual satisfaction and power consumption in a balanced way. Experimental results show that the proposed technique achieves better human visual satisfaction in terms of visuality and also shows on average 13.4% and 22.4% improvement over a prior one in terms of power saving.

A 65 nm pixel readout ASIC with quick transverse momentum discrimination capabilities for the CMS Tracker at HL-LHC

A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC . The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100 mW/cm2. The choice of a 65 nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40 MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100 μm × 1446 μm, providing 7.65 mm2 of segmented active area. Measurements of the analog front-end characteristics closely match the simulations and confirm the consumption of < 30 μA per pixel. Front-end characterization and irradiation results up to 150 MRad are also reported.

Design and Development of an RF Energy Harvesting Wireless Sensor Node (EH-WSN) for Aerospace Applications

Numerous applications of wireless sensor networks are constrained by the limited battery power of the sensors. The power consumption of processors and microcontrollers could be scaled down dramatically with the new advances in microelectronics. This reduction gives rise to the possibility of energy harvesting sources to power wireless sensor nodes. In this paper a summary is given of our ongoing research work on RF Energy Harvesting Wireless Sensor Node (EH-WSN) which can plug-in to the already developed Wireless Instrumentation System (WIS) for aerospace applications. Present WSN's which are powered from battery have limited operational lifetime. While energy harvesting has the potential to enable near-perpetual system operation, design of which is a complex trade-off due to the interaction of numerous factors such as the characteristics of the energy source, power supply requirements, power management futures, WSN application behaviour, chemistry and capacity of batteries used etc. In this work, we have identified a suitable power harvesting cum battery management scheme which harvests power consistently and deterministically from a secondary RF source which can be used even in harsh real-time applications. Using a RF power harvesting receiver IC and a compact power management cum storage circuit, we establish the test bed and conduct a series of experiments to verify the effectiveness of the proposed scheme. We have demonstrated continuous operation of the sensor node at an operating distance of 2 meters from the RF power source for a data rate of 240 sps. This is achieved by using special synchronized MAC protocol, low power techniques, usage of low leakage components and systematic coding of the micro controller firmware. This paper provides an insight into how various power reduction techniques can be used and orchestrated such that satisfactory performance can be achieved for a given energy budget.

A 2.89 μW Dry-Electrode Enabled Clockless Wireless ECG SoC for Wearable Applications

This paper presents a fully integrated wireless electrocardiogram (ECG) SoC implemented in asynchronous architecture, which does not require system clock as well as off-chip antenna. Several low power techniques are proposed to minimize power consumption. At the system level, a newly introduced event-driven system architecture facilitates the asynchronous implementation, thus removes the system clock leading to a true ECG-on-chip solution. A DC-coupled analog front-end is introduced together with a baseline stabilizer to boost the input impedance to 3.6 GQ and mitigate the electrode offset, which is less sensitive to motion artefact and contact impedance imbalance, making it well suited for dry-electrode based applications. Level-crossing analog-to-digital converter (LC-ADC) is employed to take the advantage of burst nature of ECG signal leading to at least 5 times reduction in sampling points compared to Nyquist sampling. A digitally implemented impulse-radio ultra-wideband transmitter is seamlessly integrated with LC-ADC and an on-chip antenna for wireless communications. Implemented in 0.13 μm CMOS technology, the ECG-on-chip consumes 2.89 μW under 1.2 V supply while transmitting the raw ECG data, which attains one order of magnitude lower than the current state-of-the-art designs. The fully integrated ECG SoC requires no external clocks and off-chip antenna, making it a good candidate for low cost and disposable wireless ECG patches, such as epidermal electronics.