Low-power Techniques Research Articles

Leakage Power Reduction in CMOS Logic Circuit Using Various Techniques

Low power nowadays High-power consumption has turned into a crucial design criterion for VLSI an emerging field. When it comes to energy efficiency, high power dissipation is not thought to be beneficial to battery life in the case of battery-powered applications. It reduces the efficiency, dependability, and cooling expenses of battery life. The high-frequency dynamic variation of inputs is heavily influenced by switching and short-circuit leakage power. There are several common methods for reducing the power consumption of circuits. The average power consumption consists of static and dynamic power consumption. The power consumption comparison of LECT0R, LCNT, Stack 0N0FIC, and SAP0N of various low-power techniques. These circuits are simulated in the cadence tool. Keywords: LECT0R, LCNT, Stack 0N0FIC, and SAP0N Techniques, cadence tool (90nm).

Developing a TEI-Aware PMIC for Ultra-Low-Power System-on-Chips

As the demand for ultra-low-power (ULP) devices has increased tremendously, system-on-chip (SoC) designs based on ultra-low-voltage (ULV) operation have been receiving great attention. Moreover, research has shown the remarkable potential that even more power savings can be achieved in ULV SoCs by exploiting the temperature effect inversion (TEI) phenomenon, i.e., the delay of the ULV SoCs decreases with increasing temperature. However, TEI-aware low-power (TEI-LP) techniques have a critical limitation in practical terms, in that dedicated power management-integrated circuits (PMICs) have not yet been developed. In other words, it is essential to develop PMICs that automatically bring out the full potential of the TEI-LP techniques as the chip temperature changes. With the aim of designing such PMICs, this paper first conducted a study to find the most suitable DC-DC converter for PMICs and then developed a control algorithm to maximize the effectiveness of the TEI-LP techniques. Furthermore, we have developed a compact hardware controller for the algorithm to operate most energy efficiently on ULP-SoCs.

A 900MHz GFSK and 16-FSK TX Achieving Up to 63.9% TX Efficiency and 76.2% PA Efficiency via a DC-DC-Powered Class-D VCO and a Class-E PA

This brief presents a highly efficient transmitter capable of radiating GFSK and 16-FSK modulated signals in the 900MHz ISM band. Multiple low power techniques are exploited such as a class-D VCO and a class-E single stage PA to enhance the TX efficiency. Using an on-chip DC-DC converter, the VCO can operate with down to a 250mV supply and generate 750mV signals to the input of the PA. A phased locked loop (PLL) is implemented for rapid calibration of the LO frequency and is locked to a 2MHz crystal, which also provides the clock for the DC-DC converter. The fabricated integrated circuit occupies 1mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area in 65nm LP CMOS, achieves a peak 76.2% PA efficiency and 63.9% TX efficiency, while being capable of delivering up to 3dBm to a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50\Omega $ </tex-math></inline-formula> antenna.

Phase-Based Low Power Management Combining CPU and GPU for Android Smartphones

Smartphones have limited battery capacity, so efficient power management is required for high-performance applications and to increase usage time. In recent years, efficient power management of smartphones has become very important as the demand for power use of smartphones has grown due to deep learning, games, virtual reality, and augmented reality applications. Existing low-power techniques of smartphones focus only on lowering power consumption without considering actual power consumption based on utilization of the central processing unit (CPU) and graphics processing unit (GPU), which are major components of smartphones. In addition, they do not take into consideration the strict use of resources within the component and what instructions are being processed to operate them. In this paper, we propose a low-power technique that manages power by calculating the actual power consumption of smartphones at execution time and classifying the detailed resource operating states of CPUs and GPUs. The proposed technique was implemented by linking the kernel and native app on a Galaxy S7 smartphone equipped with Android. In experiments with 15 workloads, the proposed technique achieves an energy reduction of 18.11% compared to the low-power technique of the interactive governor built into the Galaxy S7 with a small FPS reduction of 3.12%.

Event-Driven Circuits and Systems: A Promising Low Power Technique for Intelligent Sensors in AIoT Era

This brief presents an overview of current trends in the level-crossing based even-driven systems for wireless sensors in AIoT applications. We show that orders of magnitude improvement in power consumption is possible with this promising low-power technique if we have a good understanding of the operation principle of the system, the ways of processing LC samples, and the selection of LC-ADC topology. We also present the research direction to extend the event-driven system for wide applications.

A Study on SRAM Designs to Exploit the TEI-aware Ultra-low Power Techniques

Recently, temperature effect inversion aware ultra low power (TEI-ULP) techniques have been actively proposed to realize lower power above the existing ULP system-on-chips (SoCs) by utilizing the TEI phenomenon. Although these TEI-ULP techniques have been proven to have a significant power saving effect by applying them to logic parts in the actually fabricated SoC, SRAM has unfortunately been excluded from the benefits. This is because there has been no research on whether the TEI phenomenon occurs in ultra low voltage operating SRAM (ULV-SRAM) and, if so, whether the effect appears when TEI-ULP techniques are applied. In this paper, it is revealed for the first time that the TEI phenomenon occurs in the existing ULV-SRAM. In addition, this paper considers the stability problem of SRAM, which makes it difficult to apply the existing TEI-ULP techniques to ULV-SRAM, and proposes TEI-VSUS, a state-of-the-art TEI-ULP techniques to address this problem. Subsequently, this paper verifies the proposed TEI-VSUS in ULV-SRAM through intensive simulations, and the power saving rate for three representative ULV-SRAM models with different operations are acquired. Furthermore, an method to increase the power saving effect of TEIVSUS is proposed by relaxing the restrictions on stability so that the proposed technique can be used in a wider environment. The efficacy of the proposed method is also validated through simulations based on the ULV-SRAM models with the 28 nm FD-SOI process technology.

Scalable Cryoelectronics for Superconducting Qubit Control and Readout

Quantum computing promises an exponentially higher computational power than classical computers; although all the building blocks have become available, certain constraints still prevent quantum advantage. The fundamental challenge in building a practical quantum computer is integrating thousands of highly coherent qubits with the control and readout electronics. The need for a high‐coherence qubit drives the effort for quantum error correction algorithms to create fault‐tolerant quantum systems. Error correction becomes tangible in a quantum processor only in large numbers of qubits. Thus, the other challenge is reducing the number of physical interconnects (coaxial lines) between the quantum–classical interface and bulky room‐temperature electronics. To interface thousands of qubits, interconnects can be reduced by bringing the control and readout electronics near the quantum processor. Cryogenic complementary metal–oxide–semiconductor (CMOS) technology has been an ideal candidate for this purpose. Integrated control and readout at cryogenic temperatures require low power dissipation circuit designs and techniques such as frequency‐division multiplexing (FDM) due to the finite cooling power of a dilution refrigerator. Herein, an overview of each building block in a superconducting quantum computer is provided, focusing on scalability. Furthermore, this article is concluded with an outlook discussing current challenges and future directions for the scalable superconducting control and readout.

TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power

TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power

Function-oriented energy model for low power sensor nodes analysis

This work presents a new energy model based on the blocks’ functions for low power sensor nodes analysis. The procedure described generalizes the majority of low power sensor nodes applications by splitting their composing blocks into only five blocks plus the power unit. For each unit, a review of the most recent low power techniques is analyzed, as well as some of the most accepted low power principles to apply in sensor nodes. The current modeling offers a generalization since most of the existing models are application-dependent and are constrained to some fields of interest, such as wireless sensor nodes. An analytical formulation is offered, and a case study is shown as a usage example.

Power Reduction in 4T DRAM Cell Using Low Power Topologies

In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL) are implemented. A 4T DRAM cell using these low power logics has been designed and implemented. The power has been analyzed at 90nm technology. The simulation is done using the Tanner 13.1.EDA tool.

Analyzing the Effect of Uncertainty in Low Power SRAM Cells Using Artificial Intelligence Technique

This paper addresses the uncertainty that is present in the design of static random access memory (SRAM) cells using an artificial intelligence (AI) technique. The SRAM has much uncertainty in high-performance portable very large-scale integration (VLSI) chips due to their performance and storage density. This paper presents the way for solving the uncertainty problem by evaluating point-by-point recreation derived for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture for autonomous vehicles using AI algorithm. The adiabatic low power technique is implemented to enrich the configuration of the 6T-SRAM cells. The procedure of the adiabatic process will provide high loss in terms of dissipation of energy which is connected to ground (0V) and transition can be converted from ‘1’ to ‘0’. Moreover, this transition will be decreased to a high amount of degree within corresponding memory cells. Thus uncertainties with the AI model can able to deliver low power reduction using the automatic model of operation as standard adiabatic 6T SRAM cells are implemented. To prove the effectiveness in the reduction of uncertainties a low power margin is obtained with marginal values of 0.25 Volts which is much lesser than the existing models.

RISC32-LP: Low-Power FPGA-Based IoT Sensor Nodes With Energy Reduction Program Analyzer

Field-programmable gate array (FPGA)-based sensor nodes are popular for their flexible design approach and field reconfigurability. RISC32 is one of the recent Internet of Things (IoT) processors proposed for the development of FPGA-based sensor nodes, and it includes the ability to reconfigure the microarchitecture on the fly in order to reduce dynamic energy consumption. However, such a method does not minimize static energy consumption, which is important in FPGA-based systems. In this work, clock gating (CG) and dynamic voltage and frequency scaling (DVFS) are applied to further reduce the energy consumption in RISC32. In the research presented here, we implemented a new software called the energy reduction program analyzer to estimate the parameters that configure a sensor node to achieve minimum energy consumption, targeting the typical IoT application scenario. Experimental results show that the low-power techniques applied in this work (RISC32-LP) can reduce energy consumption by 47%, compared to the standard RISC32 processor.

저전력 24-GHz CMOS 믹서 설계

This paper proposes a low-power 24-GHz CMOS down-conversion mixer for the automotive radar. This circuit operates at the operation frequency of 24 GHz, and it contains low-power circuit technique. The proposed circuit is also fabricated using 65-nm RF CMOS(radio frequeny complementary metal-oxide-semiconductor) process. The circuit is powered using a 1.2-V supply with the bias voltage of 0.8 V for the low-power technique. This circuit also has fully-differential scheme to reduce RF noise, and harmonic distortions. The proposed mixer showed lower power dissipation of 6.5 mW with a high conversion gain and very small chip area of 0.01 mm2 as compared to conventional research results.

A new low-power Dynamic-GDI full adder in CNFET technology

In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit.

Study on the Effect of Gaze Position and Image Brightness on Peripheral Dimming Technique

Here, we study a low-power technique for displays based on gaze tracking, called peripheral dimming. In this work, the threshold levels of the lightness reduction ratio (LRR), where people notice differences in brightness, depending on gaze positions and image brightness, are investigated. A psychophysical experiment with five gaze positions and three image brightness conditions is performed, and the estimated threshold levels are obtained. To investigate the significance of the differences between the threshold levels, the overlap method and the Bayesian estimation (BEST) analysis are performed. The analysis results show that the difference of the threshold levels depending on the conditions is insignificant. Thus, the proposed technique can operate with a constant LRR level, regardless of the gaze position or image brightness, while maintaining the perceptual image quality. In addition, the proposed technique reduces the power consumption of virtual reality (VR) displays by 12–14% on average. We believe that the peripheral dimming technique would contribute to reducing the power of the self-luminous displays used for VR headsets with an integrated eye tracker.

A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique

PurposeIn parallel sampling method, the size of the sampling capacitor is reduced to improve the bandwidth of the ADC.Design/methodology/approachVarious low-power techniques for 10-bit 200MS/s pipelined analog-to-digital converter (ADC) are presented. This work comprises two techniques including parallel sampling and switched op-amp sharing technique.FindingsThis paper aims to study the effect of parallel sampling and switched op-amp sharing techniques on power consumption in pipelined ADC. In switched op-amp sharing technique, the numbers of op-amps used in the stages are reduced. Because of the reduction in the size of capacitors in parallel sampling technique and op-amps in the switched op-amp sharing technique, the power consumption of the proposed pipelined ADC is reduced to a greater extent.Originality/valueSimulated the 10-bit 200MS/s pipelined ADC with complementary metal oxide semiconductor process and the simulation results shows a maximum differential non-linearity of +0.31/−0.31 LSB and the maximum integral non-linearity (of +0.74/−0.74 LSB with 62.9 dB SFDR, 55.90 dB SNDR and ENOB of 8.99 bits, respectively, for 18mW power consumption with the supply voltage of 1.8 V.

TEI-DTA: Optimizing a Vehicular Sensor Network Operating with Ultra-Low Power System-on-Chips

In the era of the Internet of Things (IoT), the interest and demand for embedded systems have been explosively increasing. In particular, vehicular sensor networks are one of the fields where IoT-oriented embedded devices (also known as IoT devices) are being actively used. These IoT devices are widely deployed in and out of the vehicle to check vehicle conditions, prevent accidents, and support autonomous driving, forming a vehicular sensor network. In particular, such sensor networks mainly consist of third-party devices that operate independently of the vehicle and run on their own batteries. After all, like all battery-powered embedded devices, the IoT devices for the vehicular sensor network also suffer from limited power sources, and thus research on how to design/operate them energy-efficiently is drawing attention from both academia and industry. This paper notes that the vehicular sensor network may be the best application for ultra-low power system on-chips (ULP SoCs). The ULP SoCs are mainly designed based on ultra-low voltage operating (ULV) circuits, and this paper aims to realize the energy-optimized driving of the network by applying state of the art (SoA) low-power techniques exploiting the unique characteristics of ULV circuits to the IoT devices in the vehicular sensor network. To this end, this paper proposes an optimal task assignment algorithm that can achieve the best energy-efficient drive of the target network by fully utilizing the SoA low power techniques for ULV circuits. Along with a detailed description of the proposed algorithm, this paper demonstrates the effectiveness of the proposed method by providing an in-depth evaluation process and experimental results for the proposed algorithm.

Low-Power Wireless Sensor Network Using Fine-Grain Control of Sensor Module Power Mode.

Wireless sensor nodes are heavily resource-constrained due to their edge form factor, which has motivated increasing battery life through low-power techniques. This paper proposes a power management method that leads to less energy consumption in an idle state than conventional power management systems used in wireless sensor nodes. We analyze and benchmark the power consumption between Sleep, Idle, and Run modes. To reduce sensor node power consumption, we develop fine-grained power modes (FGPM) with five states which modulate energy consumption according to the sensor node’s communication status. We evaluate the proposed method on a test bench Mica2. As a result, the power consumed is 74.2% lower than that of conventional approaches. The proposed method targets the reduction of power consumption in IoT sensor modules with long sleep mode or short packet data in which most networks operate.

Energy-Aware Path Selection to Improve Packet Delivery Ratio and Throughput in RPL Networks

Internet of things (IoT) is a concept that motivates researchers to develop their ideas into an innovative application. RPL stands for Routing protocols for low power and lossy networks. RPL is the routing protocol, designed for constrained devices. IPv6 and Low power and Lossy network (LLN) techniques make this protocol more flexible with IoT. It is used to route the packets from the one node to another node. Various issues are observed during the routing. In RPL, Node failure, Mobility, energy consumption and congestion are few problems that are observed during the routing. The above problems lead to some issues like Packet loss, path loss, low packet delivery ratio, High energy consumption, and so on. Existing objective functions OF0 and OF1 are used in the RPL protocols to support static nodes in Destination-Oriented Directed Acyclic Graph (DODAG). In this paper, a solution is introduced to overcome node failure in RPL. The node failure in RPL is addressed by using the energy-aware routing approach in the network. The proposed technique has two mechanisms: finding the node with minimum lifetime and parent selection process. This proposed work is evaluated using COOJA simulator.

Design of 16-Bit SAR ADC Using DTMOS Technique

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.