Abstract
This article builds the confidence for undergraduate electrical/electronic engineering students in low-power very-large-scale integration by presenting a simple technique for enhancing the performance of precomputation-based content addressable memory. The proposed precomputation method provides minimal power consumption and has enhanced speed than the existing design. Experimental results were obtained using the cadence virtuoso 90 nm. The paper provides hands-on teaching in the basics of content addressable memory and low-power very-large-scale integration technique, stimulates students’ interest in very-large-scale integration, and scrutinizes pros and cons of different circuit choices.
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