FPGA based Power Efficient Binary Search for Signature Matching in Hardware NIDS

Abstract

The currently available signature matching techniques for hardware based Network Intrusion Detection System (NIDS) are using either the Content Addressable Memory (CAM) or the Hash function for fast searching. But, the CAM is consuming more power and the Hashing functions are complex. It is observed that the power consumption is a major factor in hardware architectures. Hence, we propose a power efficient searching technique using reduced Binary Search, which performs searching in the minimum locations based on the number of outgoing edges of a node in the Finite Automaton, where the signatures are compiled. This new searching approach provides fast searching with minimum power consumption when compared to CAM and Hash functions.