An Efficient Architecture Implemented to reduce the consumed power by performing Pre Reckoning using Content Addressable Memory

A Sridevi,G K D Prasanna Venkatesan,R Priyadharshini

doi:10.17485/ijst/2018/v11i19/123220

A Sridevi, G K D Prasanna Venkatesan + Show 1 more

Open Access

https://doi.org/10.17485/ijst/2018/v11i19/123220

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Abstract

Objectives: The Content Addressable Memory (CAM), are often used in various application fields to get better performance with high efficient output. The high efficient output might be obtained with minimum delay and minimum power Consumption. Methods/Statistical Analysis: The CAM is used in real time application like data search, associative computing and in the field of networking, which involves a high speed search process. A proposed banked architecture is used to control the power dissipated, which is achieved by making small variation in hardware architecture. This proposed pre reckoning -based -CAM architecture uses parameter extractor which will save the power and time. Findings: Initially parameter extractor selects the process operator, based on selected operator which will choose neighboring parameter and leaves the far away limitation. The execution of the proposed design will be done by the Xilinx software. The power consumed in every module is cumulated during execution. Application/Improvements: The obtained results also show that our choice is correct by comparing the Banking architecture with the existing one. The Proposed Banked pre reckoning architecture has minimized the average power consumption up to 30% compared with the existing one. Keywords: Banked Architecture, CAM, Parameter Extractor, Power Consumption, Pre- Reckoning

Highlights

The Content addressable memory (CAM) is a category of storage element which can be used for future processing to accumulate and to hold the data
By the results of the work, it is provided that the projected Block-XOR Pre Reckoning Based (PR)-CAM reduces the processing cycle number and it increases the bit length
With the Block XOR parameter extractor, very less power is consumed and this design minimizes the number of comparison operations

Summary

Introduction

The Content addressable memory (CAM) is a category of storage element which can be used for future processing to accumulate and to hold the data. This CAM is used in Asynchronous Transfer mode (ATM) for transferring data from individual destination to any more destinations without any distortion. The major disadvantage of this design is the CAM power consumption[1]. They may undergo several works in order to reduce match-line power and the separating the match-line power through the performance degradation.[2,3,4,5,6]

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