A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

T Kawahara,T Sakata,S Hanzawa,K Kajigaya,T Sekiguchi,R Takemura

doi:10.1109/icc.2005.1494508

A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup

T Kawahara, T Sakata + Show 4 more

https://doi.org/10.1109/icc.2005.1494508

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Publication Date: Jan 1, 2005

Affiliation: Hitachi (United Kingdom), Hitachi (Japan)

#Content-addressable Memory Architecture #Content-addressable Memory + Show 8 more

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Abstract

A new ternary/quaternary content-addressable memory (CAM) architecture using a one-hot-spot block code and two new schemes - for large-scale flow-table lookup has been developed. An NPU-side IP-address compression scheme enables a network processor unit (NPU) to track a CAM and its usage so that IP addresses can be efficiently stored with one-hot-spot block code. A dynamic re-configurable CODEC scheme enables the CAM to store both ternary and quaternary data. With 72-bit data width per word, this CAM, using 0.13-/spl mu/m stand-alone DRAM technology, can achieve 1.5 million entries, namely, six times more than a conventional static ternary CAM.

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