Low-power Memory Devices Research Articles

Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

In this work, a ferroelectric L-shaped tunnel FET (FE-LSTFET) is introduced to offer improvement in various DC and analog/high-frequency parameters. In this design, the incorporated FE layer enhances the vertical electric field at the source-channel interface, which improves the tunneling rate of charge carriers during the ON-state. The effect of negative capacitance (NC) and L-shaped N+ pocket causes dominance of vertical tunneling over corner tunneling (mainly at low gate voltages), which in turn reduces the transition voltage and current from 0.85 to 0.25 V and 1.2 × 10-8 to 5.67 × 10-11 A/µm respectively, thereby improving parameters such as ION, IOFF, and SSavg. Further, optimization of the thickness and doping concentration helps to keep the N+ pocket in fully depleted mode and consequently, ION/IOFF is increased from 0.3 × 1012 to 1.2 × 1014 and SSavg is reduced from 52 to 30 mV/decade. Subsequently, NC parameters such as remanent polarization (Pr) and coercive electric field (Ec) are optimized to increase the memory window, which further improves the read margin of FE-LSTFET as a memory device. Furthermore, TCAD-based simulation results show that optimizing the FE thickness improves ION and IOFF in the order of ∼ 1 and ∼ 2, respectively compared to those of C-LSTFET. With an optimum drain-overlap length, IOFF is shown to reduce from 6.6 × 10-17 to 5.43 × 10-19 A/µm due to a reduction in the SRH generation rate of the charge carriers. Despite the degradation in Cgg due to drain-overlap by the stack of FE and SiO2 layers, a significant increase in e-BTBT helps in achieving a transconductance of 2.48 × 10-4 S/µm, thus leading to a large cut-off frequency of 34.12 GHz. Next, analysis of the FE-LSTFET-based inverter shows significant improvements in several parameters including propagation delay and full swing. Moreover, FE-LSTFET shows more reluctance to self-heating effects than C-LSTFET as ION/IOFF is increased by an order of ∼ 3 at 500 K. Lastly, the performance of FE-LSTFET is benchmarked with existing TFET designs indicating that FE-LSTFET is suitable as a high-speed and low-power memory device.

Pulse-stream impact on recognition accuracy of reservoir computing from SiO2-based low power memory devices

Reservoir computing (RC)-based neuromorphic applications exhibit extremely low power consumption, thus challenging the use of deep neural networks in terms of both consumption requirements and integration density. Under this perspective, this work focuses on the basic principles of RC systems. The ability of self-selective conductive-bridging random access memory devices to operate in two modes, namely, volatile and non-volatile, by regulating the applied voltage is first presented. We then investigate the relaxation time of these devices as a function of the applied amplitude and pulse duration, a critical step in determining the desired non-linearity by the reservoir. Moreover, we present an in-depth study of the impact of selecting the appropriate pulse-stream and its final effects on the total power consumption and recognition accuracy in a handwritten digit recognition application from the National Institute of Standards and Technology dataset. Finally, we conclude at the optimal pulse-stream of 3-bit, through the minimization of two cost criteria, with the total power remaining at 287 µW and simultaneously achieving 82.58% recognition accuracy upon the test set.

Coexistence of Write Once Read Many Resistive Switching with Negative Differential Resistance in Bi‐Rich Bi12FeO20 Ideal Sillenite

Resistive Random-Access Memory Devices Neuromorphic devices are essential for beyond von-Neumann computing and Resistive Random Access Memories (RRAMs) are the backbone for it. In article number 2200744, Chandra Prakash and colleagues show RRAM characteristics in a Bi12FeO20 system for the first time, together with negative differential resistance (NDR) and write once and read many (WORM) like characteristics simultaneously. It is hoped this could lead to the potential of neuromorphic computing and low-power memory devices.

Cleavable crystals, crystal structure, and magnetic properties of the NbFe1+xTe3 layered van der Waals telluride.

Transition metal-based two-dimensional nanomaterials with competing magnetic states are at the cutting edge of spintronic and low-power memory devices. In this paper, we present a Fe-rich NbFe1+xTe3 layered telluride (x ≈ 0.5), which shows an interplay of spin-glass and antiferromagnetic states below the Néel temperature of 179 K. The compound has a layered crystal structure, where the NbFeTe3 layers are terminated by the Te atoms and van der Waals gaps. Bulk single crystals grown by chemical vapor transport reactions possess the (1̄01) cleavage plane suitable for the exfoliation of two-dimensional nanomaterials. Combination of high-resolution transmission electron microscopy and powder X-ray diffraction reveals the zigzag ladders of Fe atoms inside the structural layers, as well as complementary zigzag chains of the partially occupied Fe positions in the interstitial region. Fe atoms carry large effective magnetic moment of 4.85(3)μB per atom in the paramagnetic state yielding intriguing magnetic properties of NbFe1+xTe3. They include frozen spin-glass state at low temperatures and spin-flop transition in high magnetic fields indicating promising flexibility of the magnetic system and its potential control by magnetic field or gate tuning in the spintronic devices and heterostructures.

On-Chip Integrated Photonic Devices Based on Phase Change Materials

Phase change materials present a unique type of materials that drastically change their electrical and optical properties on the introduction of an external electrical or optical stimulus. Although these materials have been around for some decades, they have only recently been implemented for on-chip photonic applications. Since their reinvigoration a few years ago, on-chip devices based on phase change materials have been making a lot of progress, impacting many diverse applications at a very fast pace. At present, they are found in many interesting applications including switches and modulation; however, phase change materials are deemed most essential for next-generation low-power memory devices and neuromorphic computational platforms. This review seeks to highlight the progress thus far made in on-chip devices derived from phase change materials including memory devices, neuromorphic computing, switches, and modulators.

Infinite attractors in a chaotic circuit with exponential memristor and Josephson junction resonator

Memristors play a vital role in the design of high density and low power memory devices. Considering the complex behaviour of memristor devices because of the feature that its memductance changes with the input current, these devices finds its applications in design of nonlinear circuits. Similarly, Josephson junction resonators also exhibit complex behaviours because of its inductive properties. To model the effect of magnetic flux effects on the Josephson junction devices, we introduce the memristor to produce the feedback effect between magnetic flux and junction potential. Such a circuit produce interesting complex behaviours and hence in this paper we propose a nonlinear chaotic oscillator in a memristor-Josephson junction combination. Due to the variation laws of the flux-controlled memductance, it will not always be the same when the excitation voltage changes and hence have their drawbacks in real word applications. Considering this, we use an exponential memristor which overcomes this problem and hence can be used in physical applications. By varying the type of the bias current, we could observe the property of megastability in the memristor-Josephson junction oscillator (when excited by an AC current), which was not been observed in real physical circuits. To show the applicational benefits of the proposed oscillator, we have discussed about the synchronisation of the master-slave memristor-Josephson junction oscillators and used it in secure communication systems.

Mesoscopic origin of ferroelectric-ferroelectric transition in BaTiO3: Orthorhombic-to-tetragonal domain evolution

Ferroelectric materials are the core of common technologies, such as medical ultrasound, mobile-phone antennae and low-power memory devices. The technological interest in ferroelectrics stems from the existence of switchable mesoscale polarization domains. Hence, understanding the origin of ferroelectric functionality requires realization of the domain dynamics during a ferroelectric transformation. However, domain dynamics characterization at the mesoscale is typically too slow with respect to the abrupt ferroic transition. Using scanning probe microscopy with 15-mK thermal-, and deep-submicron spatial- resolution, we realized the domain dynamics during an orthorhombic-to-tetragonal transition in the seminal ferroelectric BaTiO3. We show that the transition comprises four distinguishable mechanisms. The dominant mechanism is a step-by-step progression of a tetragonal-domain wavefront into the orthorhombic phase. This progression is accompanied by ripple-like surface irregularities. Small island domains that remained orthorhombic diffuse then slowly after the wavefront progression. Finally, the resultant tetragonal domains equilibrate by coalescing in a constant-speed. These observations, which are accompanied by quantitative data, bridge between existing macroscopic and microscopic models regarding the nature of ferroelectric transitions, showing the mesoscale origin of ferroelectricity.

Interfacial hybridization of Janus MoSSe and BX (X = P, As) monolayers for ultrathin excitonic solar cells, nanopiezotronics and low-power memory devices.

In this work, we explored the interfacial two-dimensional (2D) physics and significant advancements in the application prospects of MoSSe monolayer when it is combined with a boron pnictide (BP, BAs) monolayer in a van der Waals heterostructure (vdWH) setup. The constructed vdWHs were found to be mechanically and dynamically stable, and they form type-II p-n heterojunctions. Thus, the photogenerated electron-hole pairs are spatially separated. In the BX/MoSSe vdWHs, the BX monolayer serves as excellent donor material for MoSSe, having an ideal donor band gap of ∼1.3 eV. The small value of the conduction band offset (CBO) between the individual monolayers in the vdWHs makes it an excellent candidate for solar energy harvesting in excitonic solar cells, where the power conversion efficiencies were calculated to be 22.97% (BP/MoSSe) and 20.86% (BAs/MoSSe). Also, more than four-fold enhancement in the out-of-plane piezoelectric coefficient (d33) was observed in the MoSSe-based vdWH relative to that in the MoS2-based vdWH owing to the intrinsic built-in vertical electric field in MoSSe. This is consistent with the out-of-plane piezoelectricity brought about by the alteration in symmetry at the metal-semiconductor Schottky junction, which has been observed experimentally [M.-M. Yang, Z.-D. Luo, Z. Mi, J. Zhao, S. P. E and M. Alexe, Nature, 2020, 584, 377-381]. The results obtained in this work provide useful insights into the design of nanomaterials for future applications in nano-optoelectronics, more efficient excitonic solar cells, and nanoelectromechanical systems (NEMS). Furthermore, this work demonstrates outstanding potential for the application of these vdWHs in superfast electronics, including low-power digital data storage and memory devices, where the tunnel current between the source and drain is effectively tunable using a normal electric field of small magnitude serving as the gate voltage.

Enhanced magnetic modulation in NiO-based memory device through ionic liquid pre-treatment

The electrical manipulation of magnetism is of particular importance owing to its potential applications in low-power memory devices and spintronics. In this study, we demonstrate enhanced magnetic modulation and an increased exchange bias field (HEB) in NiO films pretreated with ionic liquid (IL), which we refer to as IL-NiO films. The saturation magnetization of the IL-NiO film in the low-resistance state (LRS) is more than 2.5 times than that in the high-resistance state; this value is more than 80% higher than that of the NiO film without IL pretreatment (As-NiO). In addition, the HEB value of the IL-NiO film is more than 140% higher than that of the As-NiO film. Further analysis indicates that oxygen vacancies and metallic Ni0 are introduced into the NiO film during the IL pretreatment process, which results in the formation of thicker ferromagnetic Ni conductive filaments (CFs) after the set process. These thicker Ni CFs enhance the magnetism of the IL-NiO film and increase the coupling area between the ferromagnetic Ni and antiferromagnetic NiO in the LRS, thus leading to a larger magnetic modulation and higher HEB in the IL-NiO film. We believe that our findings can significantly contribute to further advancements in memory devices and allied applications.

Nanoscale Ring-Shaped Conduction Channels with Memristive Behavior in BiFeO₃ Nanodots.

Nanoscale ring-shaped conduction channels with memristive behavior have been observed in the BiFeO3 (BFO) nanodots prepared by the ion beam etching. At the hillside of each individual nanodot, a ring-shaped conduction channel is formed. Furthermore, the conduction channels exhibit memristive behavior, i.e., their resistances can be continuously tuned by the applied voltages. More specifically, a positive (negative) applied voltage reduces (increases) the resistance, and the resistance continuously varies as the repetition number of voltage scan increases. It is proposed that the surface defects distributed at the hillsides of nanodots may lower the Schottky barriers at the Pt tip/BFO interfaces, thus leading to the formation of ring-shaped conduction channels. The surface defects are formed due to the etching and they may be temporarily stabilized by the topological domain structures of BFO nanodots. In addition, the electron trapping/detrapping at the surface defects may be responsible for the memristive behavior, which is supported by the surface potential measurements. These nanoscale ring-shaped conduction channels with memristive behavior may have potential applications in high-density, low-power memory devices.

Emergence, evolution, and control of multistability in a hybrid topological quantum/classical system.

We present a novel class of nonlinear dynamical systems-a hybrid of relativistic quantum and classical systems and demonstrate that multistability is ubiquitous. A representative setting is coupled systems of a topological insulator and an insulating ferromagnet, where the former possesses an insulating bulk with topologically protected, dissipationless, and conducting surface electronic states governed by the relativistic quantum Dirac Hamiltonian and the latter is described by the nonlinear classical evolution of its magnetization vector. The interactions between the two are essentially the spin transfer torque from the topological insulator to the ferromagnet and the local proximity induced exchange coupling in the opposite direction. The hybrid system exhibits a rich variety of nonlinear dynamical phenomena besides multistability such as bifurcations, chaos, and phase synchronization. The degree of multistability can be controlled by an external voltage. In the case of two coexisting states, the system is effectively binary, opening a door to exploitation for developing spintronic memory devices. Because of the dissipationless and spin-momentum locking nature of the surface currents of the topological insulator, little power is needed for generating a significant current, making the system appealing for potential applications in next generation of low power memory devices.

Data Transmission Error Detect Scheme for High Speed Semiconductor Memory

This paper presents a code scheme for data bit error detection in the semiconductor memory devices. Conventional error detecting method by using the ATM-8 HEC code has a significant amounts of area-overhead (~700 XOR gates), and long processing time(XOR 6 stage). Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC(Cyclic Redundancy Check) calculations. The proposed error detecting scheme which is based on the parity check is improved area-overhead and decreased error detection delay time. The double bit error detection coverage has improved up to 77% compared with conventional method.

고속반도체 메모리를 위한 DBI(Data Bus Inversion)를 이용한 저비용 CRC(Cyclic Redundancy Check)방식

고속동작을 위한 반도체 메모리 제품에서 데이터의 신뢰도를 개선하기 위해 CRC(Cyclic Redundancy Check) 기능이 내장되었으며, 데이터전송 속도 개선을 위해 DBI(Data Bus Inversion) 기능이 내장되었다. DDR4, GDDR4 등의 제품에 추가된 기존의 ATM-8 HEC 코드 방식은 부가회로 면적이 크고(~XOR 700 gates) CRC 처리 시간이 길어서(XOR 6단), 저전력 메모리 제품의 데이터 읽기, 쓰기시 내부 동작 마진(margin)에 적지 않은 부담을 초래한다. 본 논문에서는 저비용, 고속 반도체 메모리에 적합한 CRC방식을 제안하였으며 92%의 부가회로가 개선되었다. 제안한 CRC방식의 저비용 구현을 위해 DBI 기능을 이용하여 데이터 비트 오류 검출율을 보완하였으며, 오류 검출율을 분석하여 기존의 CRC방식과 비교하였다. CRC function has been built into the high-speed semiconductor memory device in order to increase the reliability of data for high-speed operation. Also, DBI function is adopted to improve of data transmission speed. Conventional CRC(ATM-8 HEC code) method has a significant amounts of area-overhead(~XOR 700 gates), and processing time(6 stage XOR) is large. Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC calculations. In this paper, we propose a CRC method for low cost and high speed memory, which was improved 92% for area-overhead. For low-cost implementation of the CRC scheme by the DBI function it was supplemented by data bit error detection rate. And analyzing the error detection rate were compared with conventional CRC method.

Thermal Stability Enhancement of Cofeb Pinned Layer for Perpendicular-Magnetic Tunnel Junction with Multi-[Co/Pt]n-Synthetic-Anti-Ferro-Magnetic Layer

In recently years, research activities on magnetic tunnel junctions (MTJs) using crystalline MgO tunneling barrier layer has been performed for realizing perpendicular-spin-transfer-torque-magnetic-random-access-memory (p-STT-MRAM). In particular, to achieve perpendicular-magnetic-anisotropy (PMA) for p-MTJs grown on 12-inch TiN/W electrode, a design of synthetic-anti-ferro-magnetic (SyAF) layer being operated at the ex-tu annealing above 350 oC has been intensively studied. In general, the spin-valve has been fabricated with the structure of electrode / seed layer / CoFeB free layer / MgO tunneling barrier layer / CoFeB pinned layer / capping layer / SyAF layer / top electrode showing a high tunnel magneto-resistance ratio (TMR) of over 120 % [1]. However, the PMA characteristics of p-MTJs and the exchange coupling field (Jex) of SyAF layer degraded when the ex-tu annealing temperature increased [2]. In addition, it has been reported that non-ferro-magnetic material such as Pd in multi-[Co/Pd]nSyAF layer for spin-valves is diffused into the MgO tunneling barrier layer, deteriorating the crystallinity (L10) of the MgO tunneling barrier layer and CoFeB pinned layer after ex-tu annealing. In our paper, we investigated the thermal stability enhancement of CoFeB based p-MTJs fabricated with multi-[Co/Pt]n SyAF layer and review the mechanism by which multi-[Co/Pt]nSyAF layer enhances the thermal stability of p-MTJs.Figures 1(a), (b) and (c) show the magnetization-magnetic field (M-H) curves of multi-[Co/Pd]n SyAF layer, spin-valve structure with multi-[Co/Pd]n SyAF layer, and Pd diffusion profile analyzed using secondary-ion-mass-spectroscopy (SIMS), respectively. Pd was diffused to the MgO tunneling barrier layer after ex-tu annealing at 275 oC, as shown in Fig. 1(c). According to our previous report, Pt diffused back from the MgO tunneling barrier layer after ex-tu annealing for CoFeB based spin-valves [3]. Thus, we investigated the thermal stability enhancement by using multi-[Co/Pt]n SyAF layer rather than multi-[Co/Pd]n SyAF layer. Figures 2(a) and (b) show the dependency of the M-H curves for PMA structure and SyAF structure on Co/Pt layer thickness and ex-tu annealing temperature, respectively. The PMA characteristics of multi-[Co/Pt]n layer was degraded when the Co/Pt layer thickness and the ex-tu annealing temperature increased, as shown in Fig. 2(a). In addition, exchange coupling field of multi-[Co/Pt]n SyAF layer degraded after ex-tu annealing at 400 oC.In our presentation, we will present the thermal stability enhancement of CoFeB pinned layer for p-MTJs with multi-[Co/Pt]n SyAF layer and review the mechanism by which the thermal stability enhancement. We solved the problem of degradation of PMA and Jex of multi-[Co/Pt]n SyAF layer through more experiments. Also, we report the effect of multi-[Co/Pt]nSyAF layer spin-valves for p-MTJs as a function of annealing temperature by using vibrating-sampling-magnetometer (VSM), transmission-electron-microscopy (TEM), SIMS and current-in-plane-tunneling (CIPT) measurement. In addition, we review the mechanism why the magnetic properties of p-MTJs are varied by SyAF layer materials. * This work was financially supported by the IT R&D program of MOTIE/KEIT. [No. 10043398, Fundamental technology development of materials of magnet resistance change (MR ratio >120%) and tunneling barrier for advanced low power memory device and No. 10041608, Embedded System Software for New-memory based Smart Device] and the Brain Korea 21 plus Project in 2014, Korea. Reference [1-3] [1] S. Ikeda et al., Nature materials 9, 721-724 (2010) [2] C. Cheng et al., J. Appl. Phys., 110, 033916 (2011)[3] D. Lee et al., Appl. Phys. Lett. 102, 212409 (2013)Fig. 1. (a) M-H curves of multi-[Co/Pd]n SyAF layer : as-deposition (left) and annealed(right), (b) spin-valve structure with multi-[Co/Pd]n SyAF layer, (c) atomic component profile using SIMS profile : as-deposition (upper) and annealed (lower)Fig. 2. M-H curves depending on (a) Co/Pt layer thickness and annealing temperature for multi-[Co/Pt]n PMA structure and (b) for multi-[Co/Pt]n SyAF structure

Electrical and Optical Properties of Indium-Modified SeSbTe Thin Films for Low Power Memory Devices

The electrical and optical characteristics of indium doped Se2Sb2Te6phase-change alloy are studied. It is found that adding indium to Se2Sb2Te6 alloy (In0.3Se2Sb2Te6) increased the crystallization temperature and reduced the electrical conduction activation energy. The capacitance-temperature measurements showed a drastic change in the capacitance of the modified film when the temperature approaches the crystallization temperature, and eventually the capacitance becomes negative and nonlinear. The negativity and nonlinearity in the capacitancevoltage dependence can be attributed to the growth of conductive crystalline islands by increasing the temperature.

Ultrafast switching in nanoscale phase-change random access memory with superlattice-likestructures

Phase-change random access memory cells with superlattice-like (SLL)GeTe/Sb2Te3 were demonstrated to have excellent scaling performance in terms of switching speed andoperating voltage. In this study, the correlations between the cell size, switching speed andoperating voltage of the SLL cells were identified and investigated. We found that smallSLL cells can achieve faster switching speed and lower operating voltage compared to thelarge SLL cells. Fast amorphization and crystallization of 300 ps and 1 ns were achieved inthe 40 nm SLL cells, respectively, both significantly faster than those observed in theGe2Sb2Te5 (GST) cells of the same cell size. 40 nm SLL cells were found to switch with lowamorphization voltage of 0.9 V when pulse-widths of 5 ns were employed, which ismuch lower than the 1.6 V required by the GST cells of the same cell size. Theseeffects can be attributed to the fast heterogeneous crystallization, low thermalconductivity and high resistivity of the SLL structures. Nanoscale PCRAM with SLLstructure promises applications in high speed and low power memory devices.

Effect of annealing treatments on photoluminescence and charge storage mechanism in silicon-rich SiN x :H films

In this study, a wide range of a-SiNx:H films with an excess of silicon (20 to 50%) were prepared with an electron-cyclotron resonance plasma-enhanced chemical vapor deposition system under the flows of NH3 and SiH4. The silicon-rich a-SiNx:H films (SRSN) were sandwiched between a bottom thermal SiO2 and a top Si3N4 layer, and subsequently annealed within the temperature range of 500-1100°C in N2 to study the effect of annealing temperature on light-emitting and charge storage properties. A strong visible photoluminescence (PL) at room temperature has been observed for the as-deposited SRSN films as well as for films annealed up to 1100°C. The possible origins of the PL are briefly discussed. The authors have succeeded in the formation of amorphous Si quantum dots with an average size of about 3 to 3.6 nm by varying excess amount of Si and annealing temperature. Electrical properties have been investigated on Al/Si3N4/SRSN/SiO2/Si structures by capacitance-voltage and conductance-voltage analysis techniques. A significant memory window of 4.45 V was obtained at a low operating voltage of ± 8 V for the sample containing 25% excess silicon and annealed at 1000°C, indicating its utility in low-power memory devices.

Reproducible low-current resistive switching of metal/Pr0.7Ca0.3MnO3/Pt junctions with a point-contact top electrode

Current-voltage （I-V） and the electrical pulse induced resistive switching （EPIR）characteristics of metal/Pr0.7Ca0.3MnO3/Pt sandwich structures, where the metal is a point-contact Pt or W electrode, are investigated by using a home-made conductive AFM. The structures with both Pt and W tips behaves as rather reproducible bipolar resistive switching （RS） with an RS ratio larger than 100. However W/Pr0.7Ca0.3MnO3/Pt structures shows EPIR under a compliance current of 10 nA and reproducible bipolar RS under a compliance current of 100 pA，which is about three orders lower than the published values and shows the potential applications in low power memory device. Further analysis of I-V characteristics at different positions of sample，under different current compliances， with different contact areas of device suggests that an enhanced oxygen vacancy migration due to point contact induced local intense electrical field， gives rise to a stable RS for Pt/Pr0.7Ca0.3MnO3/Pt devices.

Recent Patents in Semiconductor Nanocluster Floating Gate Flash Memory

Nanoclusters (NC) as charge storage nodes have been applied in nonvolatile, high-speed, high-density and low-power memory devices. Compared with conventional floating gate memory, where a layer of poly-Si is used for charge storage, a memory device composed of nanoclusters isolated by dielectrics benefits from a relatively low operating voltage, high endurance, fast write-erase speeds and better immunity to soft errors due to the quantum confinement and Coulomb blockade effects. Recent patents in this field have proposed several innovated structures and fabrication methods for nanocluster based floating gate flash memory and single-electron memory devices.

Low-power memory device with NiSi2 nanocrystals embedded in silicon dioxide layer

A metal-oxide-semiconductor structure with NiSi2 nanocrystals embedded in the SiO2 layer has been fabricated. A pronounced capacitance-voltage hysteresis was observed with a memory window of 1 V under the 2 V programming voltage. The processing of the structure is compatible with the current manufacturing technology of semiconductor industry.