Data Transmission Error Detect Scheme for High Speed Semiconductor Memory

Abstract

This paper presents a code scheme for data bit error detection in the semiconductor memory devices. Conventional error detecting method by using the ATM-8 HEC code has a significant amounts of area-overhead (~700 XOR gates), and long processing time(XOR 6 stage). Therefore it leads to a considerable burden on the timing margin at the time of reading and writing of the low power memory devices for CRC(Cyclic Redundancy Check) calculations. The proposed error detecting scheme which is based on the parity check is improved area-overhead and decreased error detection delay time. The double bit error detection coverage has improved up to 77% compared with conventional method.