Implementation of Cyclic Redundancy Check in Data Recovery

Abstract

Cyclic Redundancy Check (CRC) technique can be widely used in data communication and storage devices in order to detect the sudden errors present in the data. The main motivation of this research was to detect the sudden, random or burst errors present in the transmission channels. This technique was very simple and easy to implement. It can be useful for the burst error detection and also to find the sequences of incorrect data present in the message signals. This technique was also good at detection of errors which were caused by the noise present in the transmission channels. The Conventional CRC Encoder and Decoder for 3 bits (101) and 4 bits (1100) was presented here. The proposed CRC Encoder and CRC Decoder were performed by using the binary division process and xor gate. Here, the generator or CRC polynomial or divisor was taken as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$x^{8}+x^{2}+x^{1}+1$</tex> . It can be written as 100000111 which can be referred to 9 bits of polynomial. This polynomial was kept as constant in the whole binary division process for all random data bits. The novelty of this proposed work was the implementation of both CRC Encoder and CRC Decoder for input random bits such as 5 bits (10101), 8 bits (11000011) and 10 bits (1100110011). The CRC Encoder, Decoder and Test Bench for all these random data bits were simulated, compared and verified by using Verilog coding in Xilinx ISE 14.7 tool. This proposed CRC technique was implemented in Data Recovery application. This technique can be extended to various increased data bit sizes and different generator polynomial expressions as a future scope of this research. In this work, the simulation results were limited up to 5,8 and 10 random data bits.