Parallel realization of the ATM cell header CRC

Abstract

Parallel Cyclic Redundancy Check (CRC) implementations simultaneously process multiple bits of data in parallel, increasing the data processing rate, with only a relatively small increase in the hardware complexity of serial CRC implementations that process data bit serially. This paper develops octet (8 bit), 16 bit and 32 bit parallel realizations of two serial ATM cell header CRC circuits. We show that both octet parallel ATM cell header CRC implementations can perform CRC error detection at a speed of 4 to 6 times the data processing rate of equivalent serial implementations, with the 16 and 32 bit realizations yielding even greater improvement. We also explore other practical applications of these parallel realizations, such as cell header HEC generation and cell delineation. The circuit operation of the octet parallel CRC Register ATM cell header error detection circuit and octet parallel moving window Polynomial Divider ATM cell delineation circuit has been implemented and verified experimentally in the laboratory, with the circuit operation of all other parallel realizations verified in simulation using MAX+plus II.