Low-power Logic Applications Research Articles

Spin-orbit torque magnetic tunnel junction based on 2-D materials: Impact of bias-layer on device performance

Two-dimensional (2D) material-based Spin-orbit torque (SOT) Magnetic tunnel junction (MTJ) has drawn a lot of research interest due to its potential for low power logic and memory applications. In this study, we employed a Bias-layer (BL) on top of the Topological insulator (TI) based SOT-MTJ structure to achieve field-free deterministic switching. A systematic micromagnetic simulation is carried out to examine the impact of variations in the BL-width (BW) and BL-distance (BLD) from the Free-layer (FL) on the performance parameters of the device. The stray field produced by the BL has a non-uniform profile; it declines with increase inBLD from the FL and improves with as BW increases. We demonstrate that by engineering the BLD and BW, the critical current density reduces to 3.9 × 109 A/m2, switching speed improves by 0.14 ns and power dissipation density reduces to 6.98 × 1014 Watt/m3as compared to the conventional SOT-MTJ with an external magnetic field of 100 mH.

Investigation of Field-Free Switching of 2-D Material-Based Spin–Orbit Torque Magnetic Tunnel Junction

Spin Hall-assisted magnetization switching in a three-terminal magnetic tunnel junction (MTJ) has attracted much attention due to its high-speed magnetization switching, which enables low-power memory and logic applications. In this study, 2-D materials with high spin–orbit coupling (SOC) effects and high charge-to-spin conversion efficiency are used to assess the performance characteristics of spin–orbit torque MTJ (SOT-MTJ). External field-free switching in SOT-MTJ is accomplished by employing a standard MTJ structure with a bias magnetic layer on top of the structure that projects a dipolar magnetic field onto a free layer (FL). In addition, the Dzyaloshinskii–Moriya interaction (DMI), an asymmetric exchange interaction, is considered while evaluating the critical current density. We were able to demonstrate that the required critical current density decreases by 99.5%, while the switching speed increases by 86.67% in the proposed external field-free 2-D material-based SOT-MTJ. We have also shown the significance of DMI in the field-free switching of the magnetization without the requirement for additional mechanisms when the device shrank down to the subnanometer regime.

Origin of electrically induced defects in monolayer MoS2 grown by chemical vapor deposition

Defects in MoS2 play substantial role in determining the performance of MoS2-based field-effect transistors. Typically, growth/synthesis process conditions determine the type and concentration of defects. Here, we show that defects are also introduced by prolonged operation of single crystal chemical vapor deposition-grown monolayer MoS2 transistors which hinder the overall performance. Depending on the electrical stress conditions, these defects result in threshold voltage instabilities, enhanced channel conductance, improved screening of charged impurity scattering sites and possibly better thermal management in MoS2 transistors. It turns out that a piezoelectric response in MoS2 leads to permanent change in the material’s molecular configuration thereby causing other effects like suppressed hopping transport within the channel, increased free electron concentration, prominent metal-insulator transition and reduction in channel potential with or without increasing sulfur vacancy concentration. As these defects are progressively introduced in the channel, the thermal dissipation capability of our MoS2 transistors improved due to enhanced channel-dielectric coupling. Such variations in the device performance due to spontaneous response to high electric field trigger a need to reconsider supply voltage requirements of MoS2-based electronic circuits for low-power logic applications.

Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

Floating Fin Shaped Stacked Nanosheet MOSFET for Low Power Logic Application

In this paper, floating fin structured vertically stacked nanosheet gate-all-around (GAA) metal oxide semiconductor field-effect transistor (FNS) is proposed for low power logic device applications. To verify the electrical performance of the proposed device, three-dimensional (3-D) technology computer-aided design (TCAD) device/circuit simulations are performed with calibrated device model parameters. As a result, it is found that gate propagation delay (tdelay) and dynamic power (Pdyn) are improved by 8% and 19%. respectively as compared to conventional vertically stacked lateral nanosheet (LNS). Through the rigorous analysis on the resistance and capacitance components of FNS and LNS, it is clearly revealed that the τdelay and Pdyn are improved at the same Pdyn (50 μW) and tdelay (187 GHz) by the reduced effective capacitance which results from the diminished gate-to-sorece/drain overlap area. Based on the TCAD simulation studies, it is expected that the FNS is suitable for next generation logic digital applications.

Nanometer-Thick Oxide Semiconductor Transistor with Ultra-High Drain Current.

High drive current is a critical performance parameter in semiconductor devices for high-speed, low-power logic applications or high-efficiency, high-power, high-speed radio frequency (RF) analogue applications. In this work, we demonstrate an In2O3 transistor grown by atomic layer deposition (ALD) at back-end-of-line (BEOL) compatible temperatures with a record high drain current in planar FET, exceeding 10 A/mm, the performance of which is 2-3 times better than all known transistors with semiconductor channels. A high transconductance reaches 4 S/mm, recorded among all transistors with a planar structure. Planar FETs working ballistically or quasi-ballistically are exploited as one of the simplest platforms to investigate the intrinsic transport properties. It is found experimentally and theoretically that a high carrier density and high electron velocity both contribute to this high on-state performance in ALD In2O3 transistors, which is made possible by the high-quality oxide/oxide interface, the metal-like charge-neutrality-level (CNL) alignment, and the high band velocities induced by the low density-of-state (DOS). Experimental Hall, I-V, and split C-V measurements at room temperature confirm a high carrier density of up to 6-7 × 1013 /cm2 and a high velocity of about 107 cm/s, well-supported by density functional theory (DFT) calculations. The simultaneous demonstration of such high carrier concentration and average band velocity is enabled by the exploitation of the ultrafast pulse scheme and heat dissipation engineering.

Comprehensive Study of the Current-Induced Spin-Orbit Torque Perpendicular Effective Field in Asymmetric Multilayers.

The spin–orbit torques (SOTs) in the heavy metal (HM)/ferromagnetic metal (FM) structure hold promise for next-generation low-power and high-density spintronic memory and logic applications. For the SOT switching of a perpendicular magnetization, an external magnetic field is inevitable for breaking the mirror symmetry, which is not practical for high-density nanoelectronics applications. In this work, we study the current-induced field-free SOT switching and SOT perpendicular effective field () in a variety of laterally asymmetric multilayers, where the asymmetry is introduced by growing the FM layer in a wedge shape. We show that the design of structural asymmetry by wedging the FM layer is a universal scheme for realizing field-free SOT switching. Moreover, by comparing the FM layer thickness dependence of () in different samples, we show that the efficiency (β = /J, J is the current density) is sensitive to the HM/FM interface and the FM layer thickness. The sign of β for thin FM thicknesses is related to the spin Hall angle (θSH) of the HM layer attached to the FM layer. β changes its sign with the thickness of the FM layer increasing, which may be caused by the thickness dependence of the work function of FM. These results show the possibility of engineering the deterministic field-free switching by combining the symmetry breaking and the materials design of the HM/FM interface.

Analytical modeling and TCAD simulation for subthreshold characteristics of asymmetric Tunnel FET

In this paper, a 2-D analytical model has been developed for asymmetric Tunnel FET known as Non-Uniform Body with Dual Material Source TFET (NUTFET-DMS) Device. The proposed model formulation is based on the solution of Poisson’s equation using suitable boundary conditions. The derived model for subthreshold characteristics is proposed for numerous device parameters such as surface potential, lateral, vertical electric fields, drain current and threshold voltage. In this work, for the first time the model accounts the prodigious non-uniform nature of the Channel, Gate Dielectric Thickness, Dielectric Constants and Oxide Capacitance, at different portions of the device. Next, to validate the accuracy of the model, device simulation using Sentaurus TCAD with calibrated models is reported and a close agreement with 85–95% accuracy is observed. The detailed and systematic device analysis is presented by studying different cases of applied biases, variation of device dimensions, oxide materials etc. It is reported that the proposed TFET device is able to obtain a vertical and lateral electric field of ± 5 MV/cm near the tunneling junction, implying a drain current in the order of 10−5A/μm. The present study highlights that the proposed TFET offers great potential for low standby power logic and low power applications.

Ferroelectric Devices for Intelligent Computing

Recently, transistor scaling is approaching its physical limit, hindering the further development of the computing capability. In the post-Moore era, emerging logic and storage devices have been the fundamental hardware for expanding the capability of intelligent computing. In this article, the recent progress of ferroelectric devices for intelligent computing is reviewed. The material properties and electrical characteristics of ferroelectric devices are elucidated, followed by a discussion of novel ferroelectric materials and devices that can be used for intelligent computing. Ferroelectric capacitors, transistors, and tunneling junction devices used for low-power logic, high-performance memory, and neuromorphic applications are comprehensively reviewed and compared. In addition, to provide useful guidance for developing high-performance ferroelectric-based intelligent computing systems, the key challenges for realizing ultrascaled ferroelectric devices for high-efficiency computing are discussed.

Insights into the operation of negative capacitance FinFET for low power logic applications

In the incessant search to overcome the power densities and energy efficient limitations, performance matrix of emerging electronic devices are being explored inevitably to find the alternatives of MOSFETs. We investigated and compared the delay and energy performance matrices of fin-shaped FET and negative capacitance FinFET (NC-FinFET) based devices and circuits designed on the same technology node. The improvement in the performance of NC-FinFET based CMOS circuits is enhanced due to the negative capacitance’s negative DIBL by employing a industry standard BSIM-CMG model. After analyzing at the device-level, detailed evaluation is carried out at logic level for embedded inverter chain, three-stage ring oscillators (ROs), and 2-bit ripple carry adders (RCA) for frequencies ranging between 10 kHz–1 GHz. Our findings revealed that the NC-FinFET based circuit has a lower delay for a given range of operating frequencies and saves a significant amount of power when compared to baseline FinFET, making NC-FinFET desirable for low power digital logic applications.

Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing

GaSb is considered as an attractive p-type channel material for future III-V metal-oxide-semiconductor (MOS) technologies, but the processing conditions to utilize the full device potential such as low power logic applications and RF applications still need attention. In this work, applying rapid thermal annealing (RTA) to nanoscale GaSb vertical nanowire p-type MOS field-effect transistors, we have improved the average peak transconductance (g m,peak) by 50% among 28 devices and achieved 70 μS μm−1 at V DS = −0.5 V in a device with 200 nm gate length. In addition, a low subthreshold swing down to 144 mV dec−1 as well as an off-current below 5 nA μm−1 which refers to the off-current specification in low-operation-power condition has been obtained. Based on the statistical analysis, the results show a great enhancement in both on- and off-state performance with respect to previous work mainly due to the improved electrostatics and contacts after RTA, leading to a potential in low-power logic applications. We have also examined a short channel device with L g = 80 nm in RTA, which shows an increased g m,peak up to 149 μS μm−1 at V DS = −0.5 V as well as a low on-resistance of 4.7 kΩ·μm. The potential of further enhancement in g m via RTA offers a good alternative to obtain high-performance devices for RF applications which have less stringent requirement for off-state performance. Our results indicate that post-fabrication annealing provides a great option to improve the performance of GaSb-based p-type devices with different structures for various applications.

Ferroelectricity of pure HfOx in metal-ferroelectric-insulator-semiconductor stacks and its memory application

Ferroelectricity in hafnium oxide (HfOx) and its various applications have been rigorously investigated in recent years. In particular, most studies have focused on a non-centrosymmetric ferroelectric phase that is developed via the injection of external ions into HfOx. However, the drawbacks of doped HfOx, such as serious dopant variation and thermal instability, have hindered its commercialization in low-power logic and memory applications. In this study, we demonstrated the ferroelectricity of pure HfOx without additional ion doping in metal-ferroelectric-insulator-semiconductor (MFIS) stacks. We experimentally confirmed that variation-resistant and thermally stable ferroelectric pure HfOx could be achieved with remarkable polarization by controlling the oxygen vacancies inside pure HfOx and the thermal quenching process for orthorhombic phase transition. Furthermore, to verify the feasibility of the ferroelectric pure HfOx in memory devices, the modulation of tunneling resistance was measured using MFIS ferroelectric tunnel junction (FTJ) devices, revealing that the tunneling current was adjustable over a 2-order current range via the polarization of the pure HfOx, implying that multiple current states could be obtained for multilevel memory operations.

Numerical simulations of a novel CH3NH3PbI3 based double-gate dopingless tunnel FET

Tunnel field effect transistors (TFETs) are generating considerable interest in switching applications due to their steep-subthreshold slope achieved by the quantum mechanical tunneling as a switching mechanism. However, all TFET structures currently in vogue based on Si, Ge or III–V materials have not been able to satisfy the other stringent requirements like higher on current (I ON) and low cost of fabrication. We, in this paper, report a cost-effective, organic–inorganic hybrid perovskite CH3NH3PbI3 material-based DG–DL TFET (labeled as MAPbI3–DG–DL TFET hereinafter) which has been shown to adapt to the advantages of the double gate (DG) and doping less (DL) technique for better electrostatic control and low thermal budget respectively. In simulations conducted using Silvaco Atlas tool at room temperature and supply voltage of 1 V on the proposed device structure, we have been able to achieve subthreshold swing of 27.33 mV decade−1, cut-off frequency of 0.268 THz and switching ratio of 1.85 × 1011. Detailed explanations of the results provided in the paper tend to establish that MAPbI3–DG–DL TFET could be a suitable candidate for low-power and high-speed logic applications.

Design, simulation and testing of an array of nano electro mechanical switches (NEMS)

Electro mechanical switches used for multi-purposs applications with ultra small size in nano meter scale, operating in very small voltage in millivolts, approximately zero leakage current due to air gap separation between electrodes with three terminals that easy to control it. Nano electro mechanical switches are electronic switches similar to those used by conventional semiconductor switches in application as they can be used as relays, logic devices. The basic principle of nano electro mechanical switches is electronic switches operation is fundamentally different from semiconductor switches. They have many advantages over conventional semiconductor switches such as low-power digital logic applications, ability to work with very small voltage signals for low dynamic energy consumption, and durability against hostile environments such as high temperatures and radiation contaminated spaces. In this article, we will design, implement, and test a matrix of nano electro mechanical switches by on line test using the superposition theory. The simulations of these switches were implemented using the MATLAB-Simulink and ORCAD Pspice environments. Also, controlling the flow of current was achieved by means of a nanometer movement to make or break the physical contact between the electrodes.

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Influence of Triple Material on Performance Study of Double Gate PiN Tunneling Graphene Nanoribbon FET for Low Power Logic Applications

Effectively Suppressed Short Channel Effects Use Nitrogen-Passivated of Ingaas Gate-All-Around Mosfets for High Switching Speed Logic Application

In this paper, we have fabricated an In0.53Ga0.47As gate-all-around field-effect-transistor (GAAFET) used N2 remote-plasma passivated. Transistors with Nitrogen passivated effectively suppressed short channel effect compared the controlling sample. We not only used the Nitrogen passivated but also fabricated the 9 nm top width and the near vertical sidewall of the GAA structure to enhance the gate controllability efficiency. In our results, subthreshold swing (SS) decreases from 81 to 66 mV/dec, drain induced barrier lowing (DIBL) reduces from 100 to 42 mV/V. In-situ N2 post remote plasma passivated is implemented to improve the interface of the high-k and semiconductor to suppress the short channel effect. In0.53Ga0.47As GAA FET with the Nitrogen-passivated is a promising candidate for low-power high switching speed logic application.

First-principles investigations on MXene-blue phosphorene and MXene-MoS2 transistors

In the semiconductor industry, one of the most important steps in the development of electronic devices is the discovery of electrode materials that are suitable for ohmic contact. As a newly found type of 2D materials, MXenes have been explored as materials for use in field effect transistors (FETs) with promising performances, which urges for the underlying mechanisms to be understood. In this work, the behaviors of the 5–10 nm device models for monolayer blue phosphorene (BlueP) and MoS2 with a MXene electrode are investigated using ab initio quantum transport simulations. Firstly, the interfacial properties of BlueP and MoS2 in contact with M3C2T2 (M = Ti, Zr, or Hf; T = F, OH, or O) MXene are studied. The results show that OH and some of the F functionalized MXenes form an n-type ohmic contact with BlueP or MoS2, while the O functionalized MXenes form a p-type ohmic contact with BlueP and MoS2. Accordingly, when the FET model is built with M3C2(OH)2 electrodes, these FETs exhibit high on-currents due to the ohmic contacts with subthreshold swing between 100 ∼ 200 mV/decade, and high on/off ratios up to 106 at a bias voltage of 0.5 V. Our results imply that a FET with a sub-10 nm channel length can satisfy the requirements of both high performance and low power logic applications. The results from this study indicate that MXenes may act as the appropriate electrode for high-performance BlueP and MoS2 FETs, which may provide new clues to guide the application of various 2D materials in electronics.

Hybrid-Phase-Transition FET Devices for Logic Computation

Hybrid-phase-transition FETs (HyperFETs), built by connecting a phase transition material (PTM) to the source terminal of a FET, are able to increase the ON-to- OFF current ratio. In this article, we describe a comprehensive study carried out to explore the potential of these devices for low-power and energy-limited logic applications. HyperFETs with different ON– OFF current tradeoffs are evaluated at the circuit level. The results show limited improvement over conventional transistors in terms of power and energy. However, based on this analysis, this article proposes different design techniques to overcome the drawbacks identified in the study and thereby make better use of HyperFETs. Hybrid circuits, using both FinFETs and HyperFETs, and circuits combining different HyperFET devices are introduced and evaluated. At some frequencies, reductions of over 40% were obtained with respect to FinFET-only implementations, while minimum energy per operation values were obtained, which were lower than those achieved with low standby power (LSTP) FinFETs and high-performance (HP) FinFETs. This article also evaluates the impact of PTM transition time on the power performance of HyperFET circuits.

(Invited) Manufacturable Deposition of Two-Dimensional Tungsten Disulfide for Logic Applications

The two-dimensional (2D) semiconducting molybdenum and tungsten disulfide (MoS2 and WS2) hold promise as ultra-scaled metal-oxide-semiconductor (MOS) channel material for low power and/or high-performance logic applications. Manufacturable approaches that develop highly crystalline MX2 layers, tailor the layer number down to the atomic level and remain compatible with temperature sensitive structures, are essential to unlock the desired material functionality. However, fundamental understanding is lacking on how to design chemical deposition processes for 2D MX2, such as chemical vapor deposition (CVD).Therefore, our current research efforts focus on how to control the crystallinity, structure and morphology of WS2 crystals in the first, single layer through understanding the growth behaviour during a metal-organic (MO-)CVD process. WS2 is grown from tungsten hexacarbonyl (W(CO)6) and dihydrogen sulfide (H2S) precursors on 300 mm Si substrates covered with amorphous SiO2 and on single crystalline sapphire templates. A commercial 300 mm state-of-the-art Si and SiGe epitaxial reactor has been modified to deposit MX2 materials.In order to construct a qualitative model for relevant growth processes during WS2 MOCVD, the reaction kinetics are studied. Insight in the growth mechanisms is captured from the evolution in morphology of the WS2 crystals at different stages during the MOCVD process. Based on a statistical and morphological analysis of crystals in the first, single WS2 layer, two figures of merit describing the MOCVD process are extracted: the areal density of WS2 crystals and median lateral growth rate (lateral GR in nm2/(min∙cm2)).The WS2 MOCVD process is a profoundly thermally activated deposition process, with both nucleation rate and lateral GR dependent on deposition temperature. From an Arrhenius graph of WS2 inter-nucleus distance, the activation energy of surface diffusion is 10 kcal/mole. The areal density of WS2 crystals decreases over two orders of magnitude with deposition temperature, from 2x1010 /cm2 at 550 °C to 1x108 /cm2 at 1000 °C. However, it does not vary significantly with W(CO)6 partial pressure nor ratio between chalcogen and metal precursor partial pressure. Hence, the type and areal density of active surface sites of the starting surface determines the areal density of WS2 crystals, rather than the dose of metal precursor supplied to the starting surface. This opens opportunities to further control the areal density of WS2 crystals, for example through surface pretreatment. In contrast, the lateral growth rate of WS2 crystals in first, single layer increases most profoundly with deposition temperature and metal precursor partial pressure, with an activation energy of lateral growth approaching 31 kcal/mole. From the experimentally determined activation energies, the MOCVD process is likely governed by diffusion of reagents and reaction products (e.g., CO) across the boundary layer, and the dissociative physi-sorption of W(CO)6 precursor on starting surface.Based on these insights, the MOCVD process has been optimized and WS2 crystals with a median crystal size of 500 nm have been grown on amorphous SiO2. That learning is also applied to single crystalline sapphire substrates for their epitaxial seeding capability, considered to date the preferred approach to obtain state-of-the-art intrinsic material quality. In contrast to WS2 layers on SiO2, the WS2 crystals on the pretreated sapphire substrate develop a preferential in-plane crystalline orientation. The combination of the epitaxial seeding capability with the control over the areal density of WS2 crystals down to 1.7 x109 /cm2, implies that neighboring crystals can merge without forming a defective grain boundary yielding in principle micrometer-size crystals in the first, single layer.

Suppressed threshold voltage roll-off and ambipolar transport in multilayer transition metal dichalcogenide feed-back gate transistors

The layered semiconducting transition metal dichalcogenides (s-TMDs) have attracted considerable interest as the channel material for field-effect transistors (FETs). However, the multilayer s-TMD transistors usually exhibit considerable threshold voltage (Vth) shift and ambipolar behavior at high source-drain bias, which is undesirable for modern digital electronics. Here we report the design and fabrication of double feedback gate (FBG) transistors, i.e., source FBG (S-FBG) and drain FBG (D-FBG), to combat these challenges. The FBG transistors differ from normal transistors by including an extra feedback gate, which is directly connected to the source/drain electrodes by extending and overlapping the source/drain electrodes over the yttrium oxide dielectrics on s-TMDs. We show that the S-FBG transistors based on multilayer MoS2 exhibit nearly negligible Vth roll-off at large source-drain bias, and the D-FBG multilayer WSe2 transistors could be tailored into either n-type or p-type transport, depending on the polarity of the drain bias. The double FBG structure offers an effective strategy to tailor multilayer s-TMD transistors with suppressed Vth roll-off and ambipolar transport for high-performance and low-power logic applications.