Low Pin Count Research Articles

Optimized design of an extreme low power datalogger for photovoltaic panels

<span lang="EN-US">The paper focuses on the design and implementation of a low cost and compact data logger prototype using an extreme low power (XLP) and low pin count programmable interface controllers (PIC) microcontroller using its own flash memory for the periodic data acquisition storage, while many other works focus in the Arduino Eco-system. It is planned to pick four important analog measures from the photovoltaic system, and store them directly as 10-bit numerical counts, this yields to faster data acquisition and storage (no time consuming for mathematical computation to convert each numerical count of raw data to meaningful real-world data). Avoiding the use of any kind of display and keypad, and keeping the ratio run time over sleep time as low as possible, has a maximum impact on lowering the power consumption. This prototype can be serially linked to a personal computer (PC) to view the acquisition of measurements in real time, and to retrieve all collected data through a terminal application. The experimental results are stored in comma-separated values (CSV) files to ease post data analysis with any spread sheet software, for statistical calculations and graphs drawing, in order for instance, to find the faults of the photovoltaic system and optimize its management and its performance.</span>

Improving Hardware Security on Talos II Architecture Through Boot Image Encryption

The OpenPOWER Foundation is an organization that promotes open-source high-performance hardware like the POWER9. OpenBMC is an OpenPower project that strives to produce an open-source firmware stack for Baseboard Management Controllers (BMCs). If hardware falls into the hands of competitors or bad actors, reverse engineering methods can be used to leak or manipulate sensitive information from the boot sequence. This represents a security concern because the root of trust can be invalidated. For example, since the Initial Program Load (IPL) data is frequently not encrypted and is sent over the Low Pin Count (LPC) bus, it is possible to intercept and conduct man-in-the-middle attacks to modify the boot process. The boot image flash chip could also be removed from the Talos II motherboard and examined by competing server architecture manufacturers to reveal detailed boot information. Firmware that developers deem to contain sensitive code or perform innovative operations needs to be protected before being flashed onto the boot image chip. This paper demonstrates a method to encrypt sections of the boot image by encrypting a section of the image before flashing it onto the Talos II. The encrypted image will be decrypted during the boot sequence in the Level 3 cache of the POWER9, proving that it is possible to prevent adversaries from interfering with the IPL flow or obtaining details on firmware from the flash chip. This paper presents a novel method to improve the security of the boot image on Talos II architecture by encrypting the boot firmware image and decrypting it during the boot process. The proof of concept was executed on a Raptor Engineering Talos II system running a POWER9 processor with OpenBMC firmware on the ASPEED AST2500 BMC. This research claims that this unique method increases boot time security through firmware without altering hardware.

Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing

With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture for efficient multi-site testing in semiconductors. To achieve this, the scan chain routing method is first exploited to reduce the power consumption during scan-based testing through a cluster-based approach, which is compatible with the test compression architecture. Subsequently, a new test compression architecture is proposed to encode test patterns and enable the testing of each device-under-test (DUT) through a low input test pin count by using the unique properties of the proposed tri-state detector and boundary scan architecture. The experimental results show the decrease in the test I/O requirements and test power consumption. Based on these improvements, the test application time (TAT) was significantly reduced for ISCAS'89 and IWLS'05 OpenCores benchmark circuits compared to the previous methods, without a heavy burden on the additional H/W area and routing overhead.

A Comparison of Filtering Approaches Using Low-Speed DACs for Hardware-in-the-Loop Implemented in FPGAs

The use of Hardware-in-the-Loop (HIL) systems implemented in Field Programmable Gate Arrays (FPGAs) is constantly increasing because of its advantages compared to traditional simulation techniques. This increase in usage has caused new challenges related to the improvement of their performance and features like the number of output channels, while the price of HIL systems is diminishing. At present, the use of low-speed Digital-to-Analog Converters (DACs) is starting to be a commercial possibility because of two reasons. One is their lower price and the other is their lower pin count, which determines the number and price of the FPGAs that are necessary to handle those DACs. This paper compares four filtering approaches for providing suitable data to low-speed DACs, which help to filter high-speed input signals, discarding the need of using expensive high-speed DACS, and therefore decreasing the total cost of HIL implementations. Results show that the selection of the appropriate filter should be based on the type of the input waveform and the relative importance of the dynamics versus the area.

A Single Transformer for Active Cell Equalization Method of Lithium-Ion Batteries with Two Times Fewer Secondaries than Cells

In this paper, the concept of active cell-balancing technique, by using a multiple-outputs double-forward converter for lithium-ion (Li-ion) batteries, is investigated. It controls two times more cells than secondaries, and it equalizes eight cells in a series. In this method, four secondaries can reasonably be wound with the same back electromotive force (EMF). This means a low pin count on the transformer and a low bill of materials (BOM). The bridge uses four N-channel MOSFETs as switches, which means two times fewer transistors than cells, resulting in fewer switching losses. This scheme is applied for controlling the minimum voltage among the cells of the lithium-ion battery. It uses a multi-winding transformer based on a forward double converter structure. Conventional schemes using a multi-winding transformer for electric vehicles (EVs) require an equal number of secondaries per cell. This scheme requires one secondary for two adjacent cells, thus the number of secondaries is reduced by a factor of two. Also, the redistribution of charge from a high cell to a low cell does not require many switching components and little intelligence to determine low cell voltage detection. The basic principle of this method is to use the overall battery pack voltage as a reference to supply individual cells, using a forward converter containing a transformer with a well-chosen winding ratio. The experimental and simulation results are performed to verify the feasibility of the proposed system.

IEEE 1149.7 표준 테스트 인터페이스를 사용한 핀 수 절감 테스트 기술

다양한 Intellectual Property(IP)로 이루어진 복잡한 SoC 테스트에 있어 테스트 비용 절감은 필수적이다. 본 논문에서는 IEEE Std. 1500과 IEEE Std. 1149.7 인터페이스를 사용하여 적은 수의 핀 수로 IP 기반의 System-on-a-Chip(SoC) 테스트를 가능케 하는 테스트 구조를 제안한다. IEEE Std. 1500은 IP 기반의 SoC 테스트에 있어 각 IP를 테스트할 수 있는 독립된 접근 경로를 제공한다. 본 논문에서는 이러한 독립된 테스트 경로를 IEEE Std. 1149.7로 제어 가능하도록 구성함으로서 SoC의 테스트 핀 수를 2 핀으로 줄일 수 있게 한다. 본 기술은 Wafer 및 Package 수준 테스트에 요구되는 테스트 핀 수를 줄임으로서 동시에 테스트 가능한 대상회로의 수를 늘릴 수 있고, 결과적으로 전체적인 양산 테스트 비용을 크게 절감할 수 있게 한다.

Copper Wire Bonding: R&D to High Volume Manufacturing

During the past two years copper wire bonding has entered high volume manufacturing at a number of leading edge OSATs and IDMs. Usage of copper wire has achieved 20% market share and is expected to exceed 50% within three years. Products spanning the range from low pin count devices with relatively large wire diameter to FPGA's with nearly one thousand wires at 20 μm or even 18 μm wire are now using copper wire. This paper will discuss the requirements for developing a robust copper wire bonding process and then moving it to high volume manufacturing. Process optimization begins with the selection of the appropriate wire diameter, ball diameter, bonding tool and bonding process type. These are functions not only of the bond pad opening, but also of the pad aluminum thickness and relative sensitivity of the pad to damage. Proper optimization depends on the availability of new and modified bond quality metrologies, such as extensive reliance on cross-sectioning and intermetallic coverage measurements. The bonding window of a copper wire bonding process is defined in substantially new terms compared to optimization in gold wire bonding. Once an optimized process has been developed in the lab on a single bonder, it needs to be verified. Copper wire bond processes are much less forgiving with respect to the acceptable variability on the manufacturing floor. To ensure that the process is stable, a low volume pre-manufacturing test is highly recommended. This not only makes sure that the process is stable across multiple bonders, but also ensures the adequacies of manufacturing controls, incoming materials quality and sufficient equipment calibration and maintenance procedures.

Design and implementation of a portable TPM scheme for general-purpose trusted computing based on EFI

In today's globalized digital world, network-based, mobile, and interactive collaborations have enabled work platforms of personal computers to cross multiple geographical boundaries. The new requirements of privacy-preservation, sensitive information sharing, portability, remote attestation, and robust security create new problems in system design and implementation. There are critical demands for highly secure work platforms and security enhancing mechanisms for ensuring privacy protection, component integrity, sealed storage, and remote attestation of platforms. Trusted computing is a promising technology for enhancing the security of a platform using a trusted platform module (TPM). TPM is a tamper-resistant microcontroller designed to provide robust security capabilities for computing platforms. It typically is affixed to the motherboard with a low pin count (LPC) bus. However, it limited in that TPM cannot be used directly in current common personal computers (PCs), and TPM is not flexible and portable enough to be used in different platforms because of its interface with the PC and its certificate and key structure. For these reasons, we propose a portable trusted platform module (PTPM) scheme to build a trusted platform for the common PC based on a single cryptographic chip with a universal serial bus (USB) interface and extensible firmware interface (EFI), by which platforms can get a similar degree of security protection in general-purpose systems. We show the structure of certificates and keys, which can bind to platforms via a PTPM and provide users with portability and flexibility in different platforms while still allowing the user and platform to be protected and attested. The implementation of prototype system is described in detail and the performance of the PTPM on cryptographic operations and time-costs of the system bootstrap are evaluated and analyzed. The results of experiments show that PTPM has high performances for supporting trusted computing and it can be used flexibly and portably by the user.

Advances in WLCSP Technologies to Enable Cost-Reduction

Over the past few years, Wafer Level Chip Size Packages (WLCSPs) have gained widespread adoption, due to their ability to deliver higher performance at lower or equivalent costs when compared to competing packages. WLCSPs have been an excellent fit for the handheld/portable industry, where the strong push for cost-reduction and miniaturization, coupled with relatively relaxed reliability requirements, have motivated true chip-sized packages requiring no underfill or overmold. Reliability performance initially limited the application of WLCSPs to small die sizes (<2.5mm), low pin counts (<25) and mature silicon technology nodes. Also, to date, a majority of WLCSPs have been built at a 0.5mm bump pitch, although there is increasing growth in the use of WLCSPs at 0.4mm pitch. These factors have allowed WLCSP packaging to flourish in the mixed signal and analog market space. With the maturity in this market segment, the WLCSP is beginning to transition from an advanced package to a commodity package and is subject to the price-pressure that accompanies this transition. More recently, the semiconductor industry has seen advances in WLCSP technology which have enabled the qualification envelope to be expanded to products with pin counts > 120. These advances have facilitated the use of WLCSPs for other component types such as RF, high speed, broadband and memory, many of which require advanced silicon technology nodes as well. Consequently, WLCSP is expanding to markets and applications previously supported by QFN and flip chip CSP. This expansion puts additional price and cycle time pressure on WLCSP manufacturing. The cycle time pressure is further enhanced by the changing business models and supply chain strategies adopted by companies in the new economic environment. To meet these growing market demands, WLCSP providers are faced with the challenges of providing faster cycle times and higher capacity without significant increases in capital expenditure. The above factors have driven the need for new WLCSP technologies that utilize fewer process steps compared to common WLCSP product offerings, while maintaining the robustness necessary for meeting quality and reliability requirements. Amkor is developing multiple WLCSP technology platforms to cater to the cost and performance requirements of the diverse application space. This paper will provide examples that significantly reduce overall package cost by removing photolithography layers. Each photomask layer removed saves in material costs, capital depreciation costs, overhead, and process cycle time. Materials, package size, and internal qualification vehicles are carefully chosen as part of Amkor's product introduction for the proposed process flows. This paper will examine material options, i.e., polymers and solder alloys, for these new structures and will also examine the effects of die sizes and I/O counts on product reliability. Detailed analyses of the failure modes produced during reliability testing will be coupled with mechanical simulations to enhance understanding of the failure mechanisms and to further strategies for improving product reliability.

Next Generation Nickel-Based Bond Pads Enable Copper Wire Bonding

Copper wire bonding has huge cost advantages over gold wire bonding. As a result, low pin count, heavy wire applications have already been converted to copper wire and many companies are in high volume production. Recently, with the price of gold skyrocketing, conversion of high pin count (>250 I/O), high performance applications to Cu has dramatically accelerated. These high performance devices are increasingly relying on low-k materials under the bond pads. Unfortunately, the 33% greater hardness of Cu compared to gold places even greater stress on these inherently fragile materials. This can result in difficulties with pad damage and cratering of the underlying structures. Advancements have been made to copper wire bonders, tools, and wire that have resolved many of these issues and made fine pitch copper wire bonding feasible. Ni-based bond pads have emerged to solve the pad damage problem. Nickel is about 50% harder than copper and four times harder than aluminum so that it provides greater protection against the higher stress resulting from Cu ball bonding, as well as damage during probe. This is especially beneficial for devices with low-k active circuitry under the bond pad. NiPd, NiPdAu, and/or NiAu have demonstrated their great robustness to receive the Cu wire bonding with a huge wire bonding window without any splash and with excellent reliability.

Gold Stud Bumps Flip-Chip Bonded onto Copper Electrodes with Titanium and Silver Layers

The purpose of this study was to develop the thermosonic flip-chip bonding process for gold stud bumps bonded onto copper electrodes on an alumina substrate. Copper electrodes were deposited with silver as the bonding layer and with titanium as the diffusion barrier layer. Deposition of these layers on copper electrodes improves the bonding quality between the gold stud bumps and copper electrodes. With appropriate bonding parameters, 100% bondability was achieved. Bonding strength between the gold stud bumps and copper electrodes was much higher than the value converted from the standards of the Joint Electron Device Engineering Council (JEDEC). The effects of process parameters, including bonding force, ultrasonic power, and bonding time, on bonding strength were also investigated. Experimental results indicate that bonding strength increased as bonding force and ultrasonic power increased and did not deteriorate after prolonged storage at elevated temperatures. Thus, the reliability of the high-temperature storage (HTS) test for gold stud bumps flip-chip bonded onto a silver bonding layer and titanium diffusion barrier layer is not a concern. Deposition of these two layers on copper electrodes is an effective and direct method for thermosonic flip-chip bonding of gold stud bumps to a substrate, and ensures excellent bond quality. Applications such as flip-chip bonding of chips with low pin counts or light-emitting diode (LED) packaging are appropriate.

Effect of geometry and temperature cycle on the reliability of WLCSP solder joints

The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package. A 16 I/O ADI WLCSP called MicroCSP is used as the primary test vehicle for the thermal cycling tests performed with different ramp/hold profiles. The energy-based model developed by Robert Darveaux is used to assess the reliability of solder joints.

Realization of an adaptive voltage driver for voice coil motor

In this paper we describe a head servo-positioning system for hard disk drives (HDDs), in which the usual current command for the voice coil motor has been replaced by a simpler voltage command. This solution has proven advantages in terms of cost, since the voltage driver does not require any resistive shunt for current measurement and phase-shaping passive networks for the current controller. Also, it requires a lower pin count and can be easily implemented with a PWM power stage. The voltage driver consists of a voltage-controlled power stage, with a pre-filter placed at its input, plus a back e.m.f. feed-forward compensator. The role of the pre-filter is to provide a transfer function between input signal and VCM current as close as possible to that of a standard current loop, so providing a one-to-one replacement to standard current drivers. To achieve this, it can be shown that the filter must cancel out the low-frequency pole of the VCM, located in a position which depends on the electrical impedance of the VCM itself. This, however, may change by ±30% during HDD operations, due to self-heating and consequent variation of the VCM resistance. Such variation may lead to an unsatisfactory performance of the voltage driver, so an adaptation mechanism, capable of tracking variations of VCM coil resistance, must be set up. This paper presents an on-line estimation procedure, based on an extended Kalman filter (EKF), capable of estimating the VCM coil resistance with a high degree of accuracy. EKF, however, usually brings a high computational load, making it unsuitable for real-time, low-cost embedded applications. The paper presents two reduced-order model of the VCM, for which the EKF can be implemented with 30 and 50% less computational effort, respectively, while maintaining a good estimate of the VCM coil resistance. The paper reports experimental results of VCM resistance estimation, obtained with the proposed algorithm, running in 30 μS on a 25 MHz, fixed-point DSP. Also, the on-line estimation is used to adapt the pre-filter. Experimental results show that the servo performance with adaptive voltage driver is not affected by resistance variation and equivalent to that of the standard current driver.

MicroSMD-a wafer level chip scale package

This paper outlines National Semiconductor's concept of wafer level chip scale package-also known as microSMD. This new packaging technology has been demonstrated using an 8 I/O package with 0.5 mm bump pitch, and is ideally tailored for low pin count analog and wireless devices. Product extensions to higher pin count (up to 48) are under various stages of qualification. The package construction, process flow, and package reliability are described, together with board level assembly processes and interconnect reliability.

One-pin oscillators and voltage multipliers

In today's ICs low pin count is important to save space and reduce cost. The one-pin oscillator and the on-chip voltage multiplier are, among others, two analog circuits that help to accomplish this.

A low‐cost chip size package – NuCSP

Presents a new wire bondable land grid array (LGA) chip scale package called NuCSP. NuCSP is a minimized body size wire bondable package with rigid substrate interposer. The design concept is to utilize the plating bars on the edges of the package substrate as the wire bond fingers. Bond fingers are redistributed inward to an array of plated through hole vias underneath the chip, then are connected to copper pads on the bottom of the package. NuCSP package size is about equal to die size + 3 mm. Using conventional PCB substrate manufacturing with 4/4 mils routing width/space and wire bonding process, NuCSP offers a very low cost package suitable for memory chips and low pin count application specific IC (ASIC) applications. The other advantages are that the use of wirebonding allow NuCSP be applicable for die size, pad count and pitch variations. Because it is wire bondable, NuCSP may be as generic as plastic quad flat pack (PQFP), yet providing smaller body size, lower cost and smaller package electrical parasitic parameters.

Structural and behavioral synthesis for testability techniques

In this paper, a behavioral synthesis for testability system is presented. In this system, a testability modifier is connected to an existing behavioral level synthesis program, which accepts a circuit's behavioral description in C or VHDL as input. The outline of the system is as follows: (1) a testability analyzer is first applied to identify the hard-to-test areas in the circuit from the behavioral description; (2) a selection process is then applied to select test points or partial scan flip-flops. Selection is based on behavioral information rather than low-level structural description. This allows test point insertion or partial scan usage on circuits described as an interconnection of high level modules; (3) test statement insertion (TSI), an alternative to test point insertion and partial scan, is used to modify the circuit based on the selected test points. The major advantage of using TSI is a low pin count and test application time as compared to test point insertion and partial scan. In addition, TSI can be applied at the early design phase. This approach was implemented in a computer program, and applied to several sample circuits generated by a synthesis tool. The results are also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Thin QFP — the next generation high pincount surface mount challenge

Surface mount technology has revolutionized almost all aspects of end user product development. The commercial market in Japan has used low pin count surface mount packages for many years. Europe and the United States are rapidly expanding their own surface mount manufacturing expertise.

A power-efficient channel coder/decoder chip for GSM terminals

A compact power- and computing-delay-efficient channel codec chip for the Pan-European digital cellular radio (GSM) system is presented. This key component for the hand-portable mobile station, mainly implementing GSM Recommendation 5.03 on a full duplex basis, is accomplished through a dedicated architecture and application tailored memories. An important effort was made to increase the testability of the design; the sequentiality, the low pin count, and the presence of embedded macro functions implied the need for internal scan and BIST techniques. Full scan design and self-test facilities, supported by automatic test pattern generating software, resulted in time- and coverage-efficient testing. The chip is fabricated in a double-metal 1.2- mu m CMOS technology, using a cell-based design approach incorporating memory and programmable array macro blocks. A full-rate speech channel block is decoded in less than 1.8 ms and typical average in-system power consumption does not exceed 10 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A RISC processor for embedded applications within an ASIC

The VL86C010 processor, which is well suited to RISC applications because of its small die size, low power dissipation, and low pin count, is presented. This RISC processor family was designed for maximum system performance at minimum cost, rather than maximum CPU performance at any cost. The components of the system CPU, memory controller, IO controller, and video controller were partitioned to take advantage of less-expensive plastic IC packages and, more importantly, less-expensive dynamic RAM devices (DRAMs) by using their page mode of operation. These components are described, and the processor performance is examined.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>